STRH only needs the additional operand, not t2STRH. Also invert conditional
to match the one from the load emitter above.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119911 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/ARM/ARMFastISel.cpp b/lib/Target/ARM/ARMFastISel.cpp
index c991c4e..1f93e6c 100644
--- a/lib/Target/ARM/ARMFastISel.cpp
+++ b/lib/Target/ARM/ARMFastISel.cpp
@@ -845,7 +845,6 @@
bool ARMFastISel::ARMEmitStore(EVT VT, unsigned SrcReg, Address &Addr) {
unsigned StrOpc;
bool isFloat = false;
- bool needReg0Op = false;
switch (VT.getSimpleVT().SimpleTy) {
default: return false;
case MVT::i1: {
@@ -862,7 +861,6 @@
break;
case MVT::i16:
StrOpc = isThumb ? ARM::t2STRHi12 : ARM::STRH;
- needReg0Op = true;
break;
case MVT::i32:
StrOpc = isThumb ? ARM::t2STRi12 : ARM::STRi12;
@@ -886,18 +884,16 @@
if (isFloat)
Addr.Offset /= 4;
- // FIXME: The 'needReg0Op' bit goes away once STRH is converted to
- // not use the mega-addrmode stuff.
- if (!needReg0Op)
- AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
- TII.get(StrOpc))
- .addReg(SrcReg).addReg(Addr.Base.Reg).addImm(Addr.Offset));
- else
+ // ARM::STRH needs an additional operand.
+ if (!isThumb && VT.getSimpleVT().SimpleTy == MVT::i16)
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
TII.get(StrOpc))
.addReg(SrcReg).addReg(Addr.Base.Reg)
.addReg(0).addImm(Addr.Offset));
-
+ else
+ AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
+ TII.get(StrOpc))
+ .addReg(SrcReg).addReg(Addr.Base.Reg).addImm(Addr.Offset));
return true;
}