commit 141ec63962b6fca66ab0007ffc6e50de46a22b6f
author Cameron Zwarich <zwarich@apple.com> Wed May 18 02:29:50 2011 +0000
committer Cameron Zwarich <zwarich@apple.com> Wed May 18 02:29:50 2011 +0000
tree 07b1134ff55ccdc00ca73b5c13ff01006a0dc0d3
parent 7d336c0c68f00f18c214fe5e689628f099a0f6d7

Fix typo.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131519 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/ARM/ARMISelLowering.cpp

diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp
index e3bc3fa..18d3008 100644
--- a/lib/Target/ARM/ARMISelLowering.cpp
+++ b/lib/Target/ARM/ARMISelLowering.cpp
@@ -4866,13 +4866,13 @@
 
   MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
   unsigned scratch =
-    MRI.createVirtualRegister(isThumb2 ? ARM::tGPRRegisterClass
+    MRI.createVirtualRegister(isThumb2 ? ARM::rGPRRegisterClass
                                        : ARM::GPRRegisterClass);
 
   if (isThumb2) {
-    MRI.constrainRegClass(dest, ARM::tGPRRegisterClass);
-    MRI.constrainRegClass(oldval, ARM::tGPRRegisterClass);
-    MRI.constrainRegClass(newval, ARM::tGPRRegisterClass);
+    MRI.constrainRegClass(dest, ARM::rGPRRegisterClass);
+    MRI.constrainRegClass(oldval, ARM::rGPRRegisterClass);
+    MRI.constrainRegClass(newval, ARM::rGPRRegisterClass);
   }
 
   unsigned ldrOpc, strOpc;