commit 149977b48a02735861697d5b4df1fe5a8592245f
author Vikram S. Adve <vadve@cs.uiuc.edu> Mon Aug 13 16:32:45 2001 +0000
committer Vikram S. Adve <vadve@cs.uiuc.edu> Mon Aug 13 16:32:45 2001 +0000
tree 1a6e93d9148356a805811195bd000178bb67ab99
parent b0cdcda42a99b5fb4d99c773006acb175ef391a0

Always set isDef for operand in position resultPos.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357 91177308-0d34-0410-b5e6-96231b3b80d8

lib/CodeGen/MachineInstr.cpp

diff --git a/lib/CodeGen/MachineInstr.cpp b/lib/CodeGen/MachineInstr.cpp
index 2e3f73f..85440ae 100644
--- a/lib/CodeGen/MachineInstr.cpp
+++ b/lib/CodeGen/MachineInstr.cpp
@@ -46,7 +46,8 @@
 {
   assert(i < operands.size());
   operands[i].Initialize(operandType, _val);
-  operands[i].isDef = isdef;
+  operands[i].isDef = isdef ||
+		      TargetInstrDescriptors[opCode].resultPos == (int) i;
 }
 
 void
@@ -56,7 +57,8 @@
 {
   assert(i < operands.size());
   operands[i].InitializeConst(operandType, intValue);
-  operands[i].isDef = isdef;
+  operands[i].isDef = isdef ||
+		      TargetInstrDescriptors[opCode].resultPos == (int) i;
 }
 
 void
@@ -65,7 +67,8 @@
 {
   assert(i < operands.size());
   operands[i].InitializeReg(regNum);
-  operands[i].isDef = isdef;
+  operands[i].isDef = isdef ||
+		      TargetInstrDescriptors[opCode].resultPos == (int) i;
 }
 
 void
@@ -249,9 +252,9 @@
   
   // If operand 3 (result) can be discarded, use a dead register if one exists
   if (canDiscardResult && target.zeroRegNum >= 0)
-    minstr->SetMachineOperand(resultPosition, target.zeroRegNum, true);
+    minstr->SetMachineOperand(resultPosition, target.zeroRegNum);
   else
-    minstr->SetMachineOperand(resultPosition, MachineOperand::MO_VirtualRegister, vmInstrNode->getValue(), true);
+    minstr->SetMachineOperand(resultPosition, MachineOperand::MO_VirtualRegister, vmInstrNode->getValue());
 
   return returnFlags;
 }
@@ -281,9 +284,9 @@
   
   // result operand: if it can be discarded, use a dead register if one exists
   if (canDiscardResult && target.zeroRegNum >= 0)
-    minstr->SetMachineOperand(resultPosition, target.zeroRegNum, true);
+    minstr->SetMachineOperand(resultPosition, target.zeroRegNum);
   else
-    minstr->SetMachineOperand(resultPosition, MachineOperand::MO_VirtualRegister, vmInstrNode->getValue(), true);
+    minstr->SetMachineOperand(resultPosition, MachineOperand::MO_VirtualRegister, vmInstrNode->getValue());
 }