commit 14e2cf62f43130a6ba5c4c72f83051a452633d8b
author Nate Begeman <natebegeman@mac.com> Fri Oct 14 22:06:00 2005 +0000
committer Nate Begeman <natebegeman@mac.com> Fri Oct 14 22:06:00 2005 +0000
tree 7bb4e70fd0f9f8470f1944217ca74b16cb225121
parent e0de44adba002479966943ab431f05f9384fafdd

Properly split f32 and f64 into separate register classes for scalar sse fp
fixing a bunch of nasty hackery


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23735 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/X86/X86InstrInfo.cpp

diff --git a/lib/Target/X86/X86InstrInfo.cpp b/lib/Target/X86/X86InstrInfo.cpp
index 2fec723..0f717c3 100644
--- a/lib/Target/X86/X86InstrInfo.cpp
+++ b/lib/Target/X86/X86InstrInfo.cpp
@@ -28,7 +28,7 @@
                                unsigned& destReg) const {
   MachineOpCode oc = MI.getOpcode();
   if (oc == X86::MOV8rr || oc == X86::MOV16rr || oc == X86::MOV32rr ||
-      oc == X86::FpMOV  || oc == X86::MOVAPDrr || oc == X86::MOVAPSrr) {
+      oc == X86::FpMOV  || oc == X86::MOVSSrr || oc == X86::MOVSDrr) {
       assert(MI.getNumOperands() == 2 &&
              MI.getOperand(0).isRegister() &&
              MI.getOperand(1).isRegister() &&