commit 15993f83a419950f06d2879d6701530ae6449317
author Evan Cheng <evan.cheng@apple.com> Mon Jun 27 21:26:13 2011 +0000
committer Evan Cheng <evan.cheng@apple.com> Mon Jun 27 21:26:13 2011 +0000
tree 749e4564ae6f9d1f7c3539ccec1dfd88e1642bc9
parent bea6f615eefae279e53bbb63a31d2c3c67274c45

More refactoring. Move getRegClass from TargetOperandInfo to TargetInstrInfo.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133944 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/ARM/ARMLoadStoreOptimizer.cpp

diff --git a/lib/Target/ARM/ARMLoadStoreOptimizer.cpp b/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
index f4645f1..e4ec681 100644
--- a/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
+++ b/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
@@ -1673,7 +1673,7 @@
           Ops.pop_back();
 
           const TargetInstrDesc &TID = TII->get(NewOpc);
-          const TargetRegisterClass *TRC = TID.OpInfo[0].getRegClass(TRI);
+          const TargetRegisterClass *TRC = TII->getRegClass(TID, 0, TRI);
           MRI->constrainRegClass(EvenReg, TRC);
           MRI->constrainRegClass(OddReg, TRC);