Add correct instruction encodings for vbic, vorn, and vmvn.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117282 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/ARM/ARMInstrFormats.td b/lib/Target/ARM/ARMInstrFormats.td
index 2e40d0e..c10b9ac 100644
--- a/lib/Target/ARM/ARMInstrFormats.td
+++ b/lib/Target/ARM/ARMInstrFormats.td
@@ -1698,6 +1698,15 @@
let Inst{11-7} = op11_7;
let Inst{6} = op6;
let Inst{4} = op4;
+
+ // Instruction operands.
+ bits<5> Vd;
+ bits<5> Vm;
+
+ let Inst{15-12} = Vd{3-0};
+ let Inst{22} = Vd{4};
+ let Inst{3-0} = Vm{3-0};
+ let Inst{5} = Vm{4};
}
// Same as N2V except it doesn't have a datatype suffix.
@@ -1713,6 +1722,15 @@
let Inst{11-7} = op11_7;
let Inst{6} = op6;
let Inst{4} = op4;
+
+ // Instruction operands.
+ bits<5> Vd;
+ bits<5> Vm;
+
+ let Inst{15-12} = Vd{3-0};
+ let Inst{22} = Vd{4};
+ let Inst{3-0} = Vm{3-0};
+ let Inst{5} = Vm{4};
}
// NEON 2 vector register with immediate.
diff --git a/lib/Target/ARM/ARMInstrNEON.td b/lib/Target/ARM/ARMInstrNEON.td
index 60750ed..417c48b 100644
--- a/lib/Target/ARM/ARMInstrNEON.td
+++ b/lib/Target/ARM/ARMInstrNEON.td
@@ -2899,19 +2899,22 @@
// VMVN : Vector Bitwise NOT (Immediate)
let isReMaterializable = 1 in {
+// FIXME: This instruction's encoding MAY NOT BE correct.
def VMVNv4i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 0, 1, 1, (outs DPR:$dst),
(ins nModImm:$SIMM), IIC_VMOVImm,
"vmvn", "i16", "$dst, $SIMM", "",
[(set DPR:$dst, (v4i16 (NEONvmvnImm timm:$SIMM)))]>;
+// FIXME: This instruction's encoding MAY NOT BE correct.
def VMVNv8i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 1, 1, 1, (outs QPR:$dst),
(ins nModImm:$SIMM), IIC_VMOVImm,
"vmvn", "i16", "$dst, $SIMM", "",
[(set QPR:$dst, (v8i16 (NEONvmvnImm timm:$SIMM)))]>;
-
+// FIXME: This instruction's encoding MAY NOT BE correct.
def VMVNv2i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 0, 1, 1, (outs DPR:$dst),
(ins nModImm:$SIMM), IIC_VMOVImm,
"vmvn", "i32", "$dst, $SIMM", "",
[(set DPR:$dst, (v2i32 (NEONvmvnImm timm:$SIMM)))]>;
+// FIXME: This instruction's encoding MAY NOT BE correct.
def VMVNv4i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 1, 1, 1, (outs QPR:$dst),
(ins nModImm:$SIMM), IIC_VMOVImm,
"vmvn", "i32", "$dst, $SIMM", "",