-Revert parts of 84326 and 84411. Distinquishing between fixed and non-fixed
stack slots and giving them different PseudoSourceValue's did not fix the
problem of post-alloc scheduling miscompiling llvm itself.
- Apply Dan's conservative workaround by assuming any non fixed stack slots can
alias other memory locations. This means a load from spill slot #1 cannot
move above a store of spill slot #2.
- Enable post-alloc scheduling for x86 at optimization leverl Default and above.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84424 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/ARM/ARMBaseInstrInfo.cpp b/lib/Target/ARM/ARMBaseInstrInfo.cpp
index 271e0a9..ecdf5a0 100644
--- a/lib/Target/ARM/ARMBaseInstrInfo.cpp
+++ b/lib/Target/ARM/ARMBaseInstrInfo.cpp
@@ -670,11 +670,8 @@
MachineFunction &MF = *MBB.getParent();
MachineFrameInfo &MFI = *MF.getFrameInfo();
- const Value *SV = (MFI.isFixedObjectIndex(FI) ||
- MFI.isSpillSlotObjectIndex(FI))
- ? PseudoSourceValue::getFixedStack(FI) : PseudoSourceValue::getStack();
MachineMemOperand *MMO =
- MF.getMachineMemOperand(SV,
+ MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FI),
MachineMemOperand::MOStore, 0,
MFI.getObjectSize(FI),
MFI.getObjectAlignment(FI));
@@ -711,11 +708,8 @@
MachineFunction &MF = *MBB.getParent();
MachineFrameInfo &MFI = *MF.getFrameInfo();
- const Value *SV = (MFI.isFixedObjectIndex(FI) ||
- MFI.isSpillSlotObjectIndex(FI))
- ? PseudoSourceValue::getFixedStack(FI) : PseudoSourceValue::getStack();
MachineMemOperand *MMO =
- MF.getMachineMemOperand(SV,
+ MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FI),
MachineMemOperand::MOLoad, 0,
MFI.getObjectSize(FI),
MFI.getObjectAlignment(FI));
diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp
index 2c11636..3920b38 100644
--- a/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -2225,7 +2225,7 @@
/// StoreTailCallArgumentsToStackSlot - Stores arguments to their stack slot.
static void
StoreTailCallArgumentsToStackSlot(SelectionDAG &DAG,
- SDValue Chain,
+ SDValue Chain,
const SmallVector<TailCallArgumentInfo, 8> &TailCallArgs,
SmallVector<SDValue, 8> &MemOpChains,
DebugLoc dl) {
@@ -3388,7 +3388,7 @@
// STD the extended value into the stack slot.
MachineMemOperand *MMO =
- MF.getMachineMemOperand(PseudoSourceValue::getStack(),
+ MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FrameIdx),
MachineMemOperand::MOStore, 0, 8, 8);
SDValue Ops[] = { DAG.getEntryNode(), Ext64, FIdx };
SDValue Store =
diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index 0544212..fadc818 100644
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -1562,7 +1562,7 @@
SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
SDValue Store =
DAG.getStore(Val.getValue(1), dl, Val, FIN,
- PseudoSourceValue::getStack(),
+ PseudoSourceValue::getFixedStack(RegSaveFrameIndex),
Offset);
MemOps.push_back(Store);
Offset += 8;
@@ -1765,8 +1765,9 @@
case CCValAssign::Indirect: {
// Store the argument.
SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
+ int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
- PseudoSourceValue::getStack(), 0);
+ PseudoSourceValue::getFixedStack(FI), 0);
Arg = SpillSlot;
break;
}
@@ -4867,7 +4868,7 @@
SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
StackSlot,
- PseudoSourceValue::getStack(), 0);
+ PseudoSourceValue::getFixedStack(SSFI), 0);
return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
}
@@ -4908,7 +4909,7 @@
Ops.push_back(InFlag);
Chain = DAG.getNode(X86ISD::FST, dl, Tys, &Ops[0], Ops.size());
Result = DAG.getLoad(Op.getValueType(), dl, Chain, StackSlot,
- PseudoSourceValue::getStack(), 0);
+ PseudoSourceValue::getFixedStack(SSFI), 0);
}
return Result;
@@ -5123,7 +5124,7 @@
if (isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) {
assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
Chain = DAG.getStore(Chain, dl, Value, StackSlot,
- PseudoSourceValue::getStack(), 0);
+ PseudoSourceValue::getFixedStack(SSFI), 0);
SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
SDValue Ops[] = {
Chain, StackSlot, DAG.getValueType(Op.getOperand(0).getValueType())
@@ -7718,7 +7719,6 @@
// stores were performed.
const BasicBlock *LLVM_BB = MBB->getBasicBlock();
MachineFunction *F = MBB->getParent();
- MachineFrameInfo *MFI = F->getFrameInfo();
MachineFunction::iterator MBBIter = MBB;
++MBBIter;
MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
@@ -7750,14 +7750,13 @@
}
// In the XMM save block, save all the XMM argument registers.
- const Value *SV = MFI->isFixedObjectIndex(RegSaveFrameIndex)
- ? PseudoSourceValue::getFixedStack(RegSaveFrameIndex)
- : PseudoSourceValue::getStack();
for (int i = 3, e = MI->getNumOperands(); i != e; ++i) {
int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
MachineMemOperand *MMO =
- F->getMachineMemOperand(SV, MachineMemOperand::MOStore, Offset,
- /*Size=*/16, /*Align=*/16);
+ F->getMachineMemOperand(
+ PseudoSourceValue::getFixedStack(RegSaveFrameIndex),
+ MachineMemOperand::MOStore, Offset,
+ /*Size=*/16, /*Align=*/16);
BuildMI(XMMSaveMBB, DL, TII->get(X86::MOVAPSmr))
.addFrameIndex(RegSaveFrameIndex)
.addImm(/*Scale=*/1)
diff --git a/lib/Target/X86/X86InstrBuilder.h b/lib/Target/X86/X86InstrBuilder.h
index 8cbdfec..c475b56 100644
--- a/lib/Target/X86/X86InstrBuilder.h
+++ b/lib/Target/X86/X86InstrBuilder.h
@@ -143,11 +143,8 @@
Flags |= MachineMemOperand::MOLoad;
if (TID.mayStore())
Flags |= MachineMemOperand::MOStore;
- const Value *SV = (MFI.isFixedObjectIndex(FI) ||
- MFI.isSpillSlotObjectIndex(FI))
- ? PseudoSourceValue::getFixedStack(FI) : PseudoSourceValue::getStack();
MachineMemOperand *MMO =
- MF.getMachineMemOperand(SV,
+ MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FI),
Flags, Offset,
MFI.getObjectSize(FI),
MFI.getObjectAlignment(FI));
diff --git a/lib/Target/X86/X86Subtarget.h b/lib/Target/X86/X86Subtarget.h
index 16a2f10..e9392f5 100644
--- a/lib/Target/X86/X86Subtarget.h
+++ b/lib/Target/X86/X86Subtarget.h
@@ -220,7 +220,7 @@
/// at 'More' optimization level.
bool enablePostRAScheduler(CodeGenOpt::Level OptLevel) const {
// FIXME: This causes llvm to miscompile itself on i386. :-(
- return false/*OptLevel >= CodeGenOpt::Default*/;
+ return OptLevel >= CodeGenOpt::Default;
}
};