commit 1d05ec7eeea9ef378ac0c62be5a1c8fd67bc466b
author Anton Korobeynikov <asl@math.spbu.ru> Thu Jul 16 13:45:00 2009 +0000
committer Anton Korobeynikov <asl@math.spbu.ru> Thu Jul 16 13:45:00 2009 +0000
tree 90d961ce6e17ce7a240badd892b1b0b2d0d47d34
parent 6f73af9a8766a04293ed23e20138380f73f42bb0

Add stores and truncstores

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75931 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/SystemZ/SystemZISelDAGToDAG.cpp

diff --git a/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp b/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
index 83fea60..96fcfc2 100644
--- a/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
+++ b/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
@@ -52,18 +52,19 @@
     }
 
     void dump() {
-      cerr << "SystemZRRIAddressMode " << this << "\n";
+      cerr << "SystemZRRIAddressMode " << this << '\n';
       if (BaseType == RegBase) {
         cerr << "Base.Reg ";
         if (Base.Reg.getNode() != 0) Base.Reg.getNode()->dump();
         else cerr << "nul";
+        cerr << '\n';
       } else {
-        cerr << " Base.FrameIndex " << Base.FrameIndex << "\n";
+        cerr << " Base.FrameIndex " << Base.FrameIndex << '\n';
       }
       cerr << "IndexReg ";
       if (IndexReg.getNode() != 0) IndexReg.getNode()->dump();
       else cerr << "nul";
-      cerr << " Disp " << Disp << "\n";
+      cerr << " Disp " << Disp << '\n';
     }
   };
 }

lib/Target/SystemZ/SystemZInstrInfo.td

diff --git a/lib/Target/SystemZ/SystemZInstrInfo.td b/lib/Target/SystemZ/SystemZInstrInfo.td
index 8bf4b4f..5ba96f6 100644
--- a/lib/Target/SystemZ/SystemZInstrInfo.td
+++ b/lib/Target/SystemZ/SystemZInstrInfo.td
@@ -219,6 +219,11 @@
 
 }
 
+def MOV64mr : Pseudo<(outs), (ins rriaddr:$dst, GR64:$src),
+                     "stg\t{$src, $dst}",
+                     [(store GR64:$src, rriaddr:$dst)]>;
+
+// extloads
 def MOVSX64rm8  : Pseudo<(outs GR64:$dst), (ins rriaddr:$src),
                          "lgb\t{$dst, $src}",
                          [(set GR64:$dst, (sextloadi64i8 rriaddr:$src))]>;
@@ -239,6 +244,27 @@
                          "llgf\t{$dst, $src}",
                          [(set GR64:$dst, (zextloadi64i32 rriaddr:$src))]>;
 
+// truncstores
+// FIXME: Implement 12-bit displacement stuff someday
+def MOV32m8r  : Pseudo<(outs), (ins rriaddr:$dst, GR32:$src),
+                       "stcy\t{$src, $dst}",
+                       [(truncstorei8 GR32:$src, rriaddr:$dst)]>;
+
+def MOV32m16r : Pseudo<(outs), (ins rriaddr:$dst, GR32:$src),
+                       "sthy\t{$src, $dst}",
+                       [(truncstorei16 GR32:$src, rriaddr:$dst)]>;
+
+def MOV64m8r  : Pseudo<(outs), (ins rriaddr:$dst, GR64:$src),
+                       "stcy\t{$src, $dst}",
+                       [(truncstorei8 GR64:$src, rriaddr:$dst)]>;
+
+def MOV64m16r : Pseudo<(outs), (ins rriaddr:$dst, GR64:$src),
+                       "sthy\t{$src, $dst}",
+                       [(truncstorei16 GR64:$src, rriaddr:$dst)]>;
+
+def MOV64m32r : Pseudo<(outs), (ins rriaddr:$dst, GR64:$src),
+                       "sty\t{$src, $dst}",
+                       [(truncstorei32 GR64:$src, rriaddr:$dst)]>;
 
 //===----------------------------------------------------------------------===//
 // Arithmetic Instructions