Don't need the extra register here.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111864 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/ARM/ARMFastISel.cpp b/lib/Target/ARM/ARMFastISel.cpp
index e084339..5a8fa9a 100644
--- a/lib/Target/ARM/ARMFastISel.cpp
+++ b/lib/Target/ARM/ARMFastISel.cpp
@@ -370,23 +370,21 @@
// Since the offset may be too large for the load instruction
// get the reg+offset into a register.
// TODO: Optimize this somewhat.
- // FIXME: There is more than one register class in the world...
- unsigned ScratchReg
- = FuncInfo.MF->getRegInfo().createVirtualRegister(ARM::GPRRegisterClass);
ARMCC::CondCodes Pred = ARMCC::AL;
unsigned PredReg = 0;
if (!AFI->isThumbFunction())
emitARMRegPlusImmediate(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
- ScratchReg, Reg, Offset, Pred, PredReg,
+ Reg, Reg, Offset, Pred, PredReg,
static_cast<const ARMBaseInstrInfo&>(TII));
else {
assert(AFI->isThumb2Function());
emitT2RegPlusImmediate(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
- ScratchReg, Reg, Offset, Pred, PredReg,
+ Reg, Reg, Offset, Pred, PredReg,
static_cast<const ARMBaseInstrInfo&>(TII));
}
-
+
+ // FIXME: There is more than one register class in the world...
unsigned ResultReg = createResultReg(ARM::GPRRegisterClass);
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
TII.get(ARM::LDR), ResultReg)