First patch in the direction of splitting MachineCodeEmitter in two subclasses:
JITCodeEmitter and ObjectCodeEmitter. No functional changes yet. Patch by Aaron Gray
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72631 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/ARM/ARMCodeEmitter.cpp b/lib/Target/ARM/ARMCodeEmitter.cpp
index c27fc5f..70b5d78 100644
--- a/lib/Target/ARM/ARMCodeEmitter.cpp
+++ b/lib/Target/ARM/ARMCodeEmitter.cpp
@@ -25,6 +25,7 @@
#include "llvm/Function.h"
#include "llvm/PassManager.h"
#include "llvm/CodeGen/MachineCodeEmitter.h"
+#include "llvm/CodeGen/JITCodeEmitter.h"
#include "llvm/CodeGen/MachineConstantPool.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstr.h"
@@ -41,23 +42,37 @@
STATISTIC(NumEmitted, "Number of machine instructions emitted");
namespace {
- class VISIBILITY_HIDDEN ARMCodeEmitter : public MachineFunctionPass {
+
+ class ARMCodeEmitter {
+ public:
+
+ /// getBinaryCodeForInstr - This function, generated by the
+ /// CodeEmitterGenerator using TableGen, produces the binary encoding for
+ /// machine instructions.
+
+ unsigned getBinaryCodeForInstr(const MachineInstr &MI);
+ };
+
+ template< class machineCodeEmitter>
+ class VISIBILITY_HIDDEN Emitter : public MachineFunctionPass,
+ public ARMCodeEmitter
+ {
ARMJITInfo *JTI;
const ARMInstrInfo *II;
const TargetData *TD;
TargetMachine &TM;
- MachineCodeEmitter &MCE;
+ machineCodeEmitter &MCE;
const std::vector<MachineConstantPoolEntry> *MCPEs;
const std::vector<MachineJumpTableEntry> *MJTEs;
bool IsPIC;
public:
static char ID;
- explicit ARMCodeEmitter(TargetMachine &tm, MachineCodeEmitter &mce)
+ explicit Emitter(TargetMachine &tm, machineCodeEmitter &mce)
: MachineFunctionPass(&ID), JTI(0), II(0), TD(0), TM(tm),
MCE(mce), MCPEs(0), MJTEs(0),
IsPIC(TM.getRelocationModel() == Reloc::PIC_) {}
- ARMCodeEmitter(TargetMachine &tm, MachineCodeEmitter &mce,
+ Emitter(TargetMachine &tm, machineCodeEmitter &mce,
const ARMInstrInfo &ii, const TargetData &td)
: MachineFunctionPass(&ID), JTI(0), II(&ii), TD(&td), TM(tm),
MCE(mce), MCPEs(0), MJTEs(0),
@@ -134,12 +149,6 @@
void emitMiscInstruction(const MachineInstr &MI);
- /// getBinaryCodeForInstr - This function, generated by the
- /// CodeEmitterGenerator using TableGen, produces the binary encoding for
- /// machine instructions.
- ///
- unsigned getBinaryCodeForInstr(const MachineInstr &MI);
-
/// getMachineOpValue - Return binary encoding of operand. If the machine
/// operand requires relocation, record the relocation and return zero.
unsigned getMachineOpValue(const MachineInstr &MI,const MachineOperand &MO);
@@ -161,17 +170,30 @@
void emitMachineBasicBlock(MachineBasicBlock *BB, unsigned Reloc,
intptr_t JTBase = 0);
};
- char ARMCodeEmitter::ID = 0;
+ template <class machineCodeEmitter>
+ char Emitter<machineCodeEmitter>::ID = 0;
}
/// createARMCodeEmitterPass - Return a pass that emits the collected ARM code
/// to the specified MCE object.
-FunctionPass *llvm::createARMCodeEmitterPass(ARMTargetMachine &TM,
- MachineCodeEmitter &MCE) {
- return new ARMCodeEmitter(TM, MCE);
+
+namespace llvm {
+
+FunctionPass *createARMCodeEmitterPass(
+ ARMTargetMachine &TM, MachineCodeEmitter &MCE)
+{
+ return new Emitter<MachineCodeEmitter>(TM, MCE);
+}
+FunctionPass *createARMJITCodeEmitterPass(
+ ARMTargetMachine &TM, JITCodeEmitter &JCE)
+{
+ return new Emitter<JITCodeEmitter>(TM, JCE);
}
-bool ARMCodeEmitter::runOnMachineFunction(MachineFunction &MF) {
+} // end namespace llvm
+
+template< class machineCodeEmitter>
+bool Emitter< machineCodeEmitter>::runOnMachineFunction(MachineFunction &MF) {
assert((MF.getTarget().getRelocationModel() != Reloc::Default ||
MF.getTarget().getRelocationModel() != Reloc::Static) &&
"JIT relocation model must be set to static or default!");
@@ -200,7 +222,8 @@
/// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
///
-unsigned ARMCodeEmitter::getShiftOp(unsigned Imm) const {
+template< class machineCodeEmitter>
+unsigned Emitter< machineCodeEmitter>::getShiftOp(unsigned Imm) const {
switch (ARM_AM::getAM2ShiftOpc(Imm)) {
default: assert(0 && "Unknown shift opc!");
case ARM_AM::asr: return 2;
@@ -214,7 +237,8 @@
/// getMachineOpValue - Return binary encoding of operand. If the machine
/// operand requires relocation, record the relocation and return zero.
-unsigned ARMCodeEmitter::getMachineOpValue(const MachineInstr &MI,
+template< class machineCodeEmitter>
+unsigned Emitter< machineCodeEmitter>::getMachineOpValue(const MachineInstr &MI,
const MachineOperand &MO) {
if (MO.isReg())
return ARMRegisterInfo::getRegisterNumbering(MO.getReg());
@@ -243,7 +267,8 @@
/// emitGlobalAddress - Emit the specified address to the code stream.
///
-void ARMCodeEmitter::emitGlobalAddress(GlobalValue *GV, unsigned Reloc,
+template< class machineCodeEmitter>
+void Emitter< machineCodeEmitter>::emitGlobalAddress(GlobalValue *GV, unsigned Reloc,
bool NeedStub, intptr_t ACPV) {
MCE.addRelocation(MachineRelocation::getGV(MCE.getCurrentPCOffset(),
Reloc, GV, ACPV, NeedStub));
@@ -252,7 +277,8 @@
/// emitExternalSymbolAddress - Arrange for the address of an external symbol to
/// be emitted to the current location in the function, and allow it to be PC
/// relative.
-void ARMCodeEmitter::emitExternalSymbolAddress(const char *ES, unsigned Reloc) {
+template< class machineCodeEmitter>
+void Emitter< machineCodeEmitter>::emitExternalSymbolAddress(const char *ES, unsigned Reloc) {
MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
Reloc, ES));
}
@@ -260,7 +286,8 @@
/// emitConstPoolAddress - Arrange for the address of an constant pool
/// to be emitted to the current location in the function, and allow it to be PC
/// relative.
-void ARMCodeEmitter::emitConstPoolAddress(unsigned CPI, unsigned Reloc) {
+template< class machineCodeEmitter>
+void Emitter< machineCodeEmitter>::emitConstPoolAddress(unsigned CPI, unsigned Reloc) {
// Tell JIT emitter we'll resolve the address.
MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),
Reloc, CPI, 0, true));
@@ -269,19 +296,22 @@
/// emitJumpTableAddress - Arrange for the address of a jump table to
/// be emitted to the current location in the function, and allow it to be PC
/// relative.
-void ARMCodeEmitter::emitJumpTableAddress(unsigned JTIndex, unsigned Reloc) {
+template< class machineCodeEmitter>
+void Emitter< machineCodeEmitter>::emitJumpTableAddress(unsigned JTIndex, unsigned Reloc) {
MCE.addRelocation(MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(),
Reloc, JTIndex, 0, true));
}
/// emitMachineBasicBlock - Emit the specified address basic block.
-void ARMCodeEmitter::emitMachineBasicBlock(MachineBasicBlock *BB,
+template< class machineCodeEmitter>
+void Emitter< machineCodeEmitter>::emitMachineBasicBlock(MachineBasicBlock *BB,
unsigned Reloc, intptr_t JTBase) {
MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(),
Reloc, BB, JTBase));
}
-void ARMCodeEmitter::emitWordLE(unsigned Binary) {
+template< class machineCodeEmitter>
+void Emitter< machineCodeEmitter>::emitWordLE(unsigned Binary) {
#ifndef NDEBUG
DOUT << " 0x" << std::hex << std::setw(8) << std::setfill('0')
<< Binary << std::dec << "\n";
@@ -289,7 +319,8 @@
MCE.emitWordLE(Binary);
}
-void ARMCodeEmitter::emitDWordLE(uint64_t Binary) {
+template< class machineCodeEmitter>
+void Emitter< machineCodeEmitter>::emitDWordLE(uint64_t Binary) {
#ifndef NDEBUG
DOUT << " 0x" << std::hex << std::setw(8) << std::setfill('0')
<< (unsigned)Binary << std::dec << "\n";
@@ -299,7 +330,8 @@
MCE.emitDWordLE(Binary);
}
-void ARMCodeEmitter::emitInstruction(const MachineInstr &MI) {
+template< class machineCodeEmitter>
+void Emitter< machineCodeEmitter>::emitInstruction(const MachineInstr &MI) {
DOUT << "JIT: " << (void*)MCE.getCurrentPCValue() << ":\t" << MI;
NumEmitted++; // Keep track of the # of mi's emitted
@@ -365,7 +397,8 @@
}
}
-void ARMCodeEmitter::emitConstPoolInstruction(const MachineInstr &MI) {
+template< class machineCodeEmitter>
+void Emitter< machineCodeEmitter>::emitConstPoolInstruction(const MachineInstr &MI) {
unsigned CPI = MI.getOperand(0).getImm(); // CP instruction index.
unsigned CPIndex = MI.getOperand(1).getIndex(); // Actual cp entry index.
const MachineConstantPoolEntry &MCPE = (*MCPEs)[CPIndex];
@@ -432,7 +465,8 @@
}
}
-void ARMCodeEmitter::emitMOVi2piecesInstruction(const MachineInstr &MI) {
+template< class machineCodeEmitter>
+void Emitter< machineCodeEmitter>::emitMOVi2piecesInstruction(const MachineInstr &MI) {
const MachineOperand &MO0 = MI.getOperand(0);
const MachineOperand &MO1 = MI.getOperand(1);
assert(MO1.isImm() && "Not a valid so_imm value!");
@@ -473,7 +507,8 @@
emitWordLE(Binary);
}
-void ARMCodeEmitter::emitLEApcrelJTInstruction(const MachineInstr &MI) {
+template< class machineCodeEmitter>
+void Emitter< machineCodeEmitter>::emitLEApcrelJTInstruction(const MachineInstr &MI) {
// It's basically add r, pc, (LJTI - $+8)
const TargetInstrDesc &TID = MI.getDesc();
@@ -501,7 +536,8 @@
emitWordLE(Binary);
}
-void ARMCodeEmitter::emitPseudoMoveInstruction(const MachineInstr &MI) {
+template< class machineCodeEmitter>
+void Emitter< machineCodeEmitter>::emitPseudoMoveInstruction(const MachineInstr &MI) {
unsigned Opcode = MI.getDesc().Opcode;
// Part of binary is determined by TableGn.
@@ -540,13 +576,15 @@
emitWordLE(Binary);
}
-void ARMCodeEmitter::addPCLabel(unsigned LabelID) {
+template< class machineCodeEmitter>
+void Emitter< machineCodeEmitter>::addPCLabel(unsigned LabelID) {
DOUT << " ** LPC" << LabelID << " @ "
<< (void*)MCE.getCurrentPCValue() << '\n';
JTI->addPCLabelAddr(LabelID, MCE.getCurrentPCValue());
}
-void ARMCodeEmitter::emitPseudoInstruction(const MachineInstr &MI) {
+template< class machineCodeEmitter>
+void Emitter< machineCodeEmitter>::emitPseudoInstruction(const MachineInstr &MI) {
unsigned Opcode = MI.getDesc().Opcode;
switch (Opcode) {
default:
@@ -615,8 +653,8 @@
}
}
-
-unsigned ARMCodeEmitter::getMachineSoRegOpValue(const MachineInstr &MI,
+template< class machineCodeEmitter>
+unsigned Emitter< machineCodeEmitter>::getMachineSoRegOpValue(const MachineInstr &MI,
const TargetInstrDesc &TID,
const MachineOperand &MO,
unsigned OpIdx) {
@@ -674,7 +712,8 @@
return Binary | ARM_AM::getSORegOffset(MO2.getImm()) << 7;
}
-unsigned ARMCodeEmitter::getMachineSoImmOpValue(unsigned SoImm) {
+template< class machineCodeEmitter>
+unsigned Emitter< machineCodeEmitter>::getMachineSoImmOpValue(unsigned SoImm) {
// Encode rotate_imm.
unsigned Binary = (ARM_AM::getSOImmValRot(SoImm) >> 1)
<< ARMII::SoRotImmShift;
@@ -684,7 +723,8 @@
return Binary;
}
-unsigned ARMCodeEmitter::getAddrModeSBit(const MachineInstr &MI,
+template< class machineCodeEmitter>
+unsigned Emitter< machineCodeEmitter>::getAddrModeSBit(const MachineInstr &MI,
const TargetInstrDesc &TID) const {
for (unsigned i = MI.getNumOperands(), e = TID.getNumOperands(); i != e; --i){
const MachineOperand &MO = MI.getOperand(i-1);
@@ -694,7 +734,8 @@
return 0;
}
-void ARMCodeEmitter::emitDataProcessingInstruction(const MachineInstr &MI,
+template< class machineCodeEmitter>
+void Emitter< machineCodeEmitter>::emitDataProcessingInstruction(const MachineInstr &MI,
unsigned ImplicitRd,
unsigned ImplicitRn) {
const TargetInstrDesc &TID = MI.getDesc();
@@ -757,7 +798,8 @@
emitWordLE(Binary);
}
-void ARMCodeEmitter::emitLoadStoreInstruction(const MachineInstr &MI,
+template< class machineCodeEmitter>
+void Emitter< machineCodeEmitter>::emitLoadStoreInstruction(const MachineInstr &MI,
unsigned ImplicitRd,
unsigned ImplicitRn) {
const TargetInstrDesc &TID = MI.getDesc();
@@ -831,7 +873,8 @@
emitWordLE(Binary);
}
-void ARMCodeEmitter::emitMiscLoadStoreInstruction(const MachineInstr &MI,
+template< class machineCodeEmitter>
+void Emitter< machineCodeEmitter>::emitMiscLoadStoreInstruction(const MachineInstr &MI,
unsigned ImplicitRn) {
const TargetInstrDesc &TID = MI.getDesc();
unsigned Form = TID.TSFlags & ARMII::FormMask;
@@ -914,7 +957,8 @@
return Binary;
}
-void ARMCodeEmitter::emitLoadStoreMultipleInstruction(const MachineInstr &MI) {
+template< class machineCodeEmitter>
+void Emitter< machineCodeEmitter>::emitLoadStoreMultipleInstruction(const MachineInstr &MI) {
// Part of binary is determined by TableGn.
unsigned Binary = getBinaryCodeForInstr(MI);
@@ -946,7 +990,8 @@
emitWordLE(Binary);
}
-void ARMCodeEmitter::emitMulFrmInstruction(const MachineInstr &MI) {
+template< class machineCodeEmitter>
+void Emitter< machineCodeEmitter>::emitMulFrmInstruction(const MachineInstr &MI) {
const TargetInstrDesc &TID = MI.getDesc();
// Part of binary is determined by TableGn.
@@ -983,7 +1028,8 @@
emitWordLE(Binary);
}
-void ARMCodeEmitter::emitExtendInstruction(const MachineInstr &MI) {
+template< class machineCodeEmitter>
+void Emitter< machineCodeEmitter>::emitExtendInstruction(const MachineInstr &MI) {
const TargetInstrDesc &TID = MI.getDesc();
// Part of binary is determined by TableGn.
@@ -1020,7 +1066,8 @@
emitWordLE(Binary);
}
-void ARMCodeEmitter::emitMiscArithInstruction(const MachineInstr &MI) {
+template< class machineCodeEmitter>
+void Emitter< machineCodeEmitter>::emitMiscArithInstruction(const MachineInstr &MI) {
const TargetInstrDesc &TID = MI.getDesc();
// Part of binary is determined by TableGn.
@@ -1058,7 +1105,8 @@
emitWordLE(Binary);
}
-void ARMCodeEmitter::emitBranchInstruction(const MachineInstr &MI) {
+template< class machineCodeEmitter>
+void Emitter< machineCodeEmitter>::emitBranchInstruction(const MachineInstr &MI) {
const TargetInstrDesc &TID = MI.getDesc();
if (TID.Opcode == ARM::TPsoft)
@@ -1076,7 +1124,8 @@
emitWordLE(Binary);
}
-void ARMCodeEmitter::emitInlineJumpTable(unsigned JTIndex) {
+template< class machineCodeEmitter>
+void Emitter< machineCodeEmitter>::emitInlineJumpTable(unsigned JTIndex) {
// Remember the base address of the inline jump table.
uintptr_t JTBase = MCE.getCurrentPCValue();
JTI->addJumpTableBaseAddr(JTIndex, JTBase);
@@ -1095,7 +1144,8 @@
}
}
-void ARMCodeEmitter::emitMiscBranchInstruction(const MachineInstr &MI) {
+template< class machineCodeEmitter>
+void Emitter< machineCodeEmitter>::emitMiscBranchInstruction(const MachineInstr &MI) {
const TargetInstrDesc &TID = MI.getDesc();
// Handle jump tables.
@@ -1175,7 +1225,8 @@
return Binary;
}
-void ARMCodeEmitter::emitVFPArithInstruction(const MachineInstr &MI) {
+template< class machineCodeEmitter>
+void Emitter< machineCodeEmitter>::emitVFPArithInstruction(const MachineInstr &MI) {
const TargetInstrDesc &TID = MI.getDesc();
// Part of binary is determined by TableGn.
@@ -1214,7 +1265,8 @@
emitWordLE(Binary);
}
-void ARMCodeEmitter::emitVFPConversionInstruction(const MachineInstr &MI) {
+template< class machineCodeEmitter>
+void Emitter< machineCodeEmitter>::emitVFPConversionInstruction(const MachineInstr &MI) {
const TargetInstrDesc &TID = MI.getDesc();
unsigned Form = TID.TSFlags & ARMII::FormMask;
@@ -1270,7 +1322,8 @@
emitWordLE(Binary);
}
-void ARMCodeEmitter::emitVFPLoadStoreInstruction(const MachineInstr &MI) {
+template< class machineCodeEmitter>
+void Emitter< machineCodeEmitter>::emitVFPLoadStoreInstruction(const MachineInstr &MI) {
// Part of binary is determined by TableGn.
unsigned Binary = getBinaryCodeForInstr(MI);
@@ -1304,8 +1357,8 @@
emitWordLE(Binary);
}
-void
-ARMCodeEmitter::emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI) {
+template< class machineCodeEmitter>
+void Emitter< machineCodeEmitter>::emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI) {
// Part of binary is determined by TableGn.
unsigned Binary = getBinaryCodeForInstr(MI);
@@ -1339,7 +1392,8 @@
emitWordLE(Binary);
}
-void ARMCodeEmitter::emitMiscInstruction(const MachineInstr &MI) {
+template< class machineCodeEmitter>
+void Emitter< machineCodeEmitter>::emitMiscInstruction(const MachineInstr &MI) {
// Part of binary is determined by TableGn.
unsigned Binary = getBinaryCodeForInstr(MI);
@@ -1350,3 +1404,4 @@
}
#include "ARMGenCodeEmitter.inc"
+