Fix the opcode and the operands for the load instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111885 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/ARM/ARMFastISel.cpp b/lib/Target/ARM/ARMFastISel.cpp
index 2247b85..a1b9eb4 100644
--- a/lib/Target/ARM/ARMFastISel.cpp
+++ b/lib/Target/ARM/ARMFastISel.cpp
@@ -415,10 +415,13 @@
}
// FIXME: There is more than one register class in the world...
+ // TODO: Verify the additions above work, otherwise we'll need to add the
+ // offset instead of 0 and do all sorts of operand munging.
unsigned ResultReg = createResultReg(FixedRC);
+ unsigned Opc = AFI->isThumb2Function() ? ARM::tLDR : ARM::LDR;
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
- TII.get(ARM::LDR), ResultReg)
- .addImm(0).addReg(Reg).addImm(Offset));
+ TII.get(Opc), ResultReg)
+ .addReg(Reg).addReg(0).addImm(0));
UpdateValueMap(I, ResultReg);
return true;