commit 234bb38d6c421ea22229087a9835afe99e531276
author Hal Finkel <hfinkel@anl.gov> Wed Dec 07 06:34:06 2011 +0000
committer Hal Finkel <hfinkel@anl.gov> Wed Dec 07 06:34:06 2011 +0000
tree f058fcd30e4b5e41b36a4e9f594baa29cd1c0f14
parent 6d0e014b1fecb35a06e551165614c08edc30194a

make CR spill and restore 64-bit clean (no functional change), and fix some other problems found with -verify-machineinstrs

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146024 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/PowerPC/PPCAsmPrinter.cpp

diff --git a/lib/Target/PowerPC/PPCAsmPrinter.cpp b/lib/Target/PowerPC/PPCAsmPrinter.cpp
index a33dfda..5dc2d3d 100644
--- a/lib/Target/PowerPC/PPCAsmPrinter.cpp
+++ b/lib/Target/PowerPC/PPCAsmPrinter.cpp
@@ -365,11 +365,12 @@
   }
       
   case PPC::MFCRpseud:
+  case PPC::MFCR8pseud:
     // Transform: %R3 = MFCRpseud %CR7
     // Into:      %R3 = MFCR      ;; cr7
     OutStreamer.AddComment(PPCInstPrinter::
                            getRegisterName(MI->getOperand(1).getReg()));
-    TmpInst.setOpcode(PPC::MFCR);
+    TmpInst.setOpcode(Subtarget.isPPC64() ? PPC::MFCR8 : PPC::MFCR);
     TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
     OutStreamer.EmitInstruction(TmpInst);
     return;