Handle IMPLICIT_DEF with isUndef operand marker, part 2. This patch moves the code to annotate machineoperands to LiveIntervalAnalysis. It also add markers for implicit_def that define physical registers. The rest, is just a lot of details.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74580 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/CellSPU/SPUInstrInfo.cpp b/lib/Target/CellSPU/SPUInstrInfo.cpp
index 4af995a..e629c8d 100644
--- a/lib/Target/CellSPU/SPUInstrInfo.cpp
+++ b/lib/Target/CellSPU/SPUInstrInfo.cpp
@@ -491,19 +491,22 @@
if (OpNum == 0) { // move -> store
unsigned InReg = MI->getOperand(1).getReg();
bool isKill = MI->getOperand(1).isKill();
+ bool isUndef = MI->getOperand(1).isUndef();
if (FrameIndex < SPUFrameInfo::maxFrameOffset()) {
MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(),
get(SPU::STQDr32));
- MIB.addReg(InReg, getKillRegState(isKill));
+ MIB.addReg(InReg, getKillRegState(isKill) | getUndefRegState(isUndef));
NewMI = addFrameReference(MIB, FrameIndex);
}
} else { // move -> load
unsigned OutReg = MI->getOperand(0).getReg();
bool isDead = MI->getOperand(0).isDead();
+ bool isUndef = MI->getOperand(0).isUndef();
MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc));
- MIB.addReg(OutReg, RegState::Define | getDeadRegState(isDead));
+ MIB.addReg(OutReg, RegState::Define | getDeadRegState(isDead) |
+ getUndefRegState(isUndef));
Opc = (FrameIndex < SPUFrameInfo::maxFrameOffset())
? SPU::STQDr32 : SPU::STQXr32;
NewMI = addFrameReference(MIB, FrameIndex);