Continue to tighten decoding by performing more operand validation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137340 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
index d599422..8cfb217 100644
--- a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
+++ b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
@@ -133,6 +133,8 @@
uint64_t Address, const void *Decoder);
static bool DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder);
+static bool DecodeMSRMask(llvm::MCInst &Inst, unsigned Insn,
+ uint64_t Address, const void *Decoder);
static bool DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn,
@@ -759,6 +761,8 @@
static bool DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder) {
+ // Empty register lists are not allowed.
+ if (CountPopulation_32(Val) == 0) return false;
for (unsigned i = 0; i < 16; ++i) {
if (Val & (1 << i)) {
if (!DecodeGPRRegisterClass(Inst, i, Address, Decoder)) return false;
@@ -2467,3 +2471,9 @@
return true;
}
+static bool DecodeMSRMask(llvm::MCInst &Inst, unsigned Val,
+ uint64_t Address, const void *Decoder) {
+ if (!Val) return false;
+ Inst.addOperand(MCOperand::CreateImm(Val));
+ return true;
+}