commit 2dc74dd831c611895bf5ac66521b4d944b15cc0b
author Chris Lattner <sabre@nondot.org> Sun Oct 23 05:47:52 2005 +0000
committer Chris Lattner <sabre@nondot.org> Sun Oct 23 05:47:52 2005 +0000
tree dc8acd337cb7dce9bb2e2e6c9431daac38e9a9d5
parent ba76c21858bac5fd953d4dbe2f0624d8e884c7b5

Remove the obsolete instr selector emitter


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23894 91177308-0d34-0410-b5e6-96231b3b80d8

utils/TableGen/TableGen.cpp

diff --git a/utils/TableGen/TableGen.cpp b/utils/TableGen/TableGen.cpp
index d356e57..5d946c2 100644
--- a/utils/TableGen/TableGen.cpp
+++ b/utils/TableGen/TableGen.cpp
@@ -23,7 +23,6 @@
 #include "RegisterInfoEmitter.h"
 #include "InstrInfoEmitter.h"
 #include "AsmWriterEmitter.h"
-#include "InstrSelectorEmitter.h"
 #include "DAGISelEmitter.h"
 #include "SubtargetEmitter.h"
 #include <algorithm>
@@ -35,7 +34,7 @@
   PrintRecords,
   GenEmitter,
   GenRegisterEnums, GenRegister, GenRegisterHeader,
-  GenInstrEnums, GenInstrs, GenAsmWriter, GenInstrSelector,
+  GenInstrEnums, GenInstrs, GenAsmWriter, 
   GenDAGISel,
   GenSubtarget,
   PrintEnums,
@@ -61,8 +60,6 @@
                                "Generate instruction descriptions"),
                     clEnumValN(GenAsmWriter, "gen-asm-writer",
                                "Generate assembly writer"),
-                    clEnumValN(GenInstrSelector, "gen-instr-selector",
-                               "Generate an instruction selector"),
                     clEnumValN(GenDAGISel, "gen-dag-isel",
                                "Generate a DAG instruction selector"),
                     clEnumValN(GenSubtarget, "gen-subtarget",
@@ -470,9 +467,6 @@
       AsmWriterEmitter(Records).run(*Out);
       break;
 
-    case GenInstrSelector:
-      InstrSelectorEmitter(Records).run(*Out);
-      break;
     case GenDAGISel:
       DAGISelEmitter(Records).run(*Out);
       break;