Add RA to the set of registers that are defined if instruction is a call.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141194 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/Mips/MipsDelaySlotFiller.cpp b/lib/Target/Mips/MipsDelaySlotFiller.cpp
index 059c111..b8443c1 100644
--- a/lib/Target/Mips/MipsDelaySlotFiller.cpp
+++ b/lib/Target/Mips/MipsDelaySlotFiller.cpp
@@ -218,13 +218,13 @@
SmallSet<unsigned, 32>& RegDefs,
SmallSet<unsigned, 32>& RegUses) {
// If MI is a call or return, just examine the explicit non-variadic operands.
- // NOTE: $ra is not added to RegDefs, since currently $ra is reserved and
- // no instruction that can possibly be put in a delay slot can read or
- // write it.
-
MCInstrDesc MCID = MI->getDesc();
unsigned e = MCID.isCall() || MCID.isReturn() ? MCID.getNumOperands() :
MI->getNumOperands();
+
+ // Add RA to RegDefs to prevent users of RA from going into delay slot.
+ if (MCID.isCall())
+ RegDefs.insert(Mips::RA);
for (unsigned i = 0; i != e; ++i) {
const MachineOperand &MO = MI->getOperand(i);