| commit | 306d14f9aa9fe6891f5df447fe9e0a380de02501 | [log] [tgz] |
|---|---|---|
| author | Chris Lattner <sabre@nondot.org> | Mon Oct 19 23:31:43 2009 +0000 |
| committer | Chris Lattner <sabre@nondot.org> | Mon Oct 19 23:31:43 2009 +0000 |
| tree | fd374a310b952e650b55009a905235237706bb25 | |
| parent | 84d8bf9d28a1a8ce9314d6286f1c5c1d10aefc6c [diff] [blame] |
handle addmode4 modifiers, fix a fixme in printRegisterList by ignoring all implicit regs when lowering. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84566 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/ARM/AsmPrinter/ARMMCInstLower.cpp b/lib/Target/ARM/AsmPrinter/ARMMCInstLower.cpp index 45e61de..cda5555 100644 --- a/lib/Target/ARM/AsmPrinter/ARMMCInstLower.cpp +++ b/lib/Target/ARM/AsmPrinter/ARMMCInstLower.cpp
@@ -118,6 +118,8 @@ MI->dump(); assert(0 && "unknown operand type"); case MachineOperand::MO_Register: + // Ignore all implicit register operands. + if (MO.isImplicit()) continue; MCOp = MCOperand::CreateReg(MO.getReg()); break; case MachineOperand::MO_Immediate: