Extend InlineAsm::C_Register to allow multiple specific registers
(actually, code already all worked, only the comment
changed). Use this to implement 'A' constraint on x86.
Fixes PR 1779.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59266 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index 221f29f..2348191 100644
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -7542,6 +7542,7 @@
if (Constraint.size() == 1) {
switch (Constraint[0]) {
case 'A':
+ return C_Register;
case 'f':
case 'r':
case 'R':
@@ -7671,10 +7672,6 @@
// FIXME: not handling fp-stack yet!
switch (Constraint[0]) { // GCC X86 Constraint Letters
default: break; // Unknown constraint letter
- case 'A': // EAX/EDX
- if (VT == MVT::i32 || VT == MVT::i64)
- return make_vector<unsigned>(X86::EAX, X86::EDX, 0);
- break;
case 'q': // Q_REGS (GENERAL_REGS in 64-bit mode)
case 'Q': // Q_REGS
if (VT == MVT::i32)
@@ -7762,7 +7759,11 @@
Res.first = X86::ST0;
Res.second = X86::RFP80RegisterClass;
}
-
+ // 'A' means EAX + EDX.
+ if (Constraint == "A") {
+ Res.first = X86::EAX;
+ Res.second = X86::GRADRegisterClass;
+ }
return Res;
}
diff --git a/lib/Target/X86/X86RegisterInfo.td b/lib/Target/X86/X86RegisterInfo.td
index 5228b76..4ddec00 100644
--- a/lib/Target/X86/X86RegisterInfo.td
+++ b/lib/Target/X86/X86RegisterInfo.td
@@ -440,6 +440,27 @@
let SubRegClassList = [GR8, GR16];
}
+// A class to support the 'A' assembler constraint: EAX then EDX.
+def GRAD : RegisterClass<"X86", [i32], 32, [EAX, EDX]> {
+ let MethodProtos = [{
+ iterator allocation_order_begin(const MachineFunction &MF) const;
+ iterator allocation_order_end(const MachineFunction &MF) const;
+ }];
+
+ let MethodBodies = [{
+ static const unsigned X86_GRAD_AO[] = {X86::EAX, X86::EDX};
+ GRADClass::iterator
+ GRADClass::allocation_order_begin(const MachineFunction &MF) const {
+ return X86_GRAD_AO;
+ }
+
+ GRADClass::iterator
+ GRADClass::allocation_order_end(const MachineFunction &MF) const {
+ return X86_GRAD_AO + (sizeof(X86_GRAD_AO) / sizeof(unsigned));
+ }
+ }];
+}
+
// Scalar SSE2 floating point registers.
def FR32 : RegisterClass<"X86", [f32], 32,
[XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,