Push GPRnopc through a large number of instruction definitions to tighten operand decoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137189 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
index 59bed8d..acd1a41 100644
--- a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
+++ b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
@@ -1177,10 +1177,10 @@
if (pred == 0xF)
return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
- DecodeGPRRegisterClass(Inst, Rd, Address, Decoder);
- DecodeGPRRegisterClass(Inst, Rn, Address, Decoder);
- DecodeGPRRegisterClass(Inst, Rm, Address, Decoder);
- DecodeGPRRegisterClass(Inst, Ra, Address, Decoder);
+ DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder);
+ DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder);
+ DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder);
+ DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder);
return true;
}