Tighten operand checking on CPS instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137172 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
index d7b8856..a3fa138 100644
--- a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
+++ b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
@@ -83,6 +83,8 @@
const void *Decoder);
static bool DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder);
+static bool DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn,
+ uint64_t Address, const void *Decoder);
static bool DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder);
static bool DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val,
@@ -1139,6 +1141,9 @@
unsigned iflags = fieldFromInstruction32(Insn, 6, 3);
unsigned mode = fieldFromInstruction32(Insn, 0, 5);
+ // imod == '01' --> UNPREDICTABLE
+ if (imod == 1) return false;
+
if (M && mode && imod && iflags) {
Inst.setOpcode(ARM::CPS3p);
Inst.addOperand(MCOperand::CreateImm(imod));