commit 358829f1510031794ed9419ac869ab31c31c337f
author Misha Brukman <brukman+llvm@gmail.com> Mon Jun 21 17:25:55 2004 +0000
committer Misha Brukman <brukman+llvm@gmail.com> Mon Jun 21 17:25:55 2004 +0000
tree 6bde97bf44ce626dc8867f20131ee1f9c6a1f9e8
parent d71bd56caa4bddc1219584fce81af6e8a53c85a1

Type::getPrimitiveID() -> getTypeID()


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14288 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/PowerPC/PowerPCISelSimple.cpp

diff --git a/lib/Target/PowerPC/PowerPCISelSimple.cpp b/lib/Target/PowerPC/PowerPCISelSimple.cpp
index c9c0e2d..af5e16e 100644
--- a/lib/Target/PowerPC/PowerPCISelSimple.cpp
+++ b/lib/Target/PowerPC/PowerPCISelSimple.cpp
@@ -39,7 +39,7 @@
 /// size of the type, and whether or not it is floating point.
 ///
 static inline TypeClass getClass(const Type *Ty) {
-  switch (Ty->getPrimitiveID()) {
+  switch (Ty->getTypeID()) {
   case Type::SByteTyID:
   case Type::UByteTyID:   return cByte;      // Byte operands are class #0
   case Type::ShortTyID:
@@ -2306,7 +2306,7 @@
 	}
 
     unsigned TmpReg = makeAnotherReg(Type::IntTy);
-    switch (SrcTy->getPrimitiveID()) {
+    switch (SrcTy->getTypeID()) {
     case Type::BoolTyID:
     case Type::SByteTyID:
       BuildMI(*BB, IP, PPC32::EXTSB, 1, TmpReg).addReg(SrcReg);
@@ -2411,7 +2411,7 @@
   unsigned DestReg = getReg(I);
 
   unsigned Size;
-  switch (I.getArgType()->getPrimitiveID()) {
+  switch (I.getArgType()->getTypeID()) {
   default:
     std::cerr << I;
     assert(0 && "Error: bad type for va_next instruction!");
@@ -2436,7 +2436,7 @@
   unsigned VAList = getReg(I.getOperand(0));
   unsigned DestReg = getReg(I);
 
-  switch (I.getType()->getPrimitiveID()) {
+  switch (I.getType()->getTypeID()) {
   default:
     std::cerr << I;
     assert(0 && "Error: bad type for va_next instruction!");