commit 35c33bd772b3cfb34fdc6b5c9171f955454d0043
author Chris Lattner <sabre@nondot.org> Sun Apr 04 04:47:45 2010 +0000
committer Chris Lattner <sabre@nondot.org> Sun Apr 04 04:47:45 2010 +0000
tree 763442764850298ab7321ad5b68be659d9fb60cf
parent 20adc9dc4650313f017b27d9818eb2176238113d

change a ton of code to not implicitly use the "O" raw_ostream
member of AsmPrinter.  Instead, pass it in explicitly.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100306 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/X86/AsmPrinter/X86IntelInstPrinter.cpp

diff --git a/lib/Target/X86/AsmPrinter/X86IntelInstPrinter.cpp b/lib/Target/X86/AsmPrinter/X86IntelInstPrinter.cpp
index 610beb5..e12b148 100644
--- a/lib/Target/X86/AsmPrinter/X86IntelInstPrinter.cpp
+++ b/lib/Target/X86/AsmPrinter/X86IntelInstPrinter.cpp
@@ -28,14 +28,17 @@
 #include "X86GenAsmWriter1.inc"
 #undef MachineInstr
 
-void X86IntelInstPrinter::printInst(const MCInst *MI) { printInstruction(MI); }
+void X86IntelInstPrinter::printInst(const MCInst *MI) {
+  printInstruction(MI, O);
+}
 StringRef X86IntelInstPrinter::getOpcodeName(unsigned Opcode) const {
   return getInstructionName(Opcode);
 }
 
-void X86IntelInstPrinter::printSSECC(const MCInst *MI, unsigned Op) {
+void X86IntelInstPrinter::printSSECC(const MCInst *MI, unsigned Op,
+                                     raw_ostream &O) {
   switch (MI->getOperand(Op).getImm()) {
-  default: llvm_unreachable("Invalid ssecc argument!");
+  default: assert(0 && "Invalid ssecc argument!");
   case 0: O << "eq"; break;
   case 1: O << "lt"; break;
   case 2: O << "le"; break;
@@ -49,7 +52,8 @@
 
 /// print_pcrel_imm - This is used to print an immediate value that ends up
 /// being encoded as a pc-relative value.
-void X86IntelInstPrinter::print_pcrel_imm(const MCInst *MI, unsigned OpNo) {
+void X86IntelInstPrinter::print_pcrel_imm(const MCInst *MI, unsigned OpNo,
+                                          raw_ostream &O) {
   const MCOperand &Op = MI->getOperand(OpNo);
   if (Op.isImm())
     O << Op.getImm();
@@ -65,9 +69,7 @@
 }
 
 void X86IntelInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
-                                     const char *Modifier) {
-  assert(Modifier == 0 && "Modifiers should not be used");
-  
+                                       raw_ostream &O) {
   const MCOperand &Op = MI->getOperand(OpNo);
   if (Op.isReg()) {
     PrintRegName(O, getRegisterName(Op.getReg()));
@@ -79,7 +81,8 @@
   }
 }
 
-void X86IntelInstPrinter::printLeaMemReference(const MCInst *MI, unsigned Op) {
+void X86IntelInstPrinter::printLeaMemReference(const MCInst *MI, unsigned Op,
+                                               raw_ostream &O) {
   const MCOperand &BaseReg  = MI->getOperand(Op);
   unsigned ScaleVal         = MI->getOperand(Op+1).getImm();
   const MCOperand &IndexReg = MI->getOperand(Op+2);
@@ -89,7 +92,7 @@
   
   bool NeedPlus = false;
   if (BaseReg.getReg()) {
-    printOperand(MI, Op);
+    printOperand(MI, Op, O);
     NeedPlus = true;
   }
   
@@ -97,7 +100,7 @@
     if (NeedPlus) O << " + ";
     if (ScaleVal != 1)
       O << ScaleVal << '*';
-    printOperand(MI, Op+2);
+    printOperand(MI, Op+2, O);
     NeedPlus = true;
   }
   
@@ -124,11 +127,12 @@
   O << ']';
 }
 
-void X86IntelInstPrinter::printMemReference(const MCInst *MI, unsigned Op) {
+void X86IntelInstPrinter::printMemReference(const MCInst *MI, unsigned Op,
+                                            raw_ostream &O) {
   // If this has a segment register, print it.
   if (MI->getOperand(Op+4).getReg()) {
-    printOperand(MI, Op+4);
+    printOperand(MI, Op+4, O);
     O << ':';
   }
-  printLeaMemReference(MI, Op);
+  printLeaMemReference(MI, Op, O);
 }