make UpdateValueMap handle the possiblity that we could be
copying into the right register, avoiding a copy.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68889 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/CodeGen/SelectionDAG/FastISel.cpp b/lib/CodeGen/SelectionDAG/FastISel.cpp
index 7e30053..251e96a 100644
--- a/lib/CodeGen/SelectionDAG/FastISel.cpp
+++ b/lib/CodeGen/SelectionDAG/FastISel.cpp
@@ -158,7 +158,7 @@
unsigned &AssignedReg = ValueMap[I];
if (AssignedReg == 0)
AssignedReg = Reg;
- else {
+ else if (Reg != AssignedReg) {
const TargetRegisterClass *RegClass = MRI.getRegClass(Reg);
TII.copyRegToReg(*MBB, MBB->end(), AssignedReg,
Reg, RegClass, RegClass);