commit 38e59891ee4417a9be2f8146ce0ba3269e38ac21
author Benjamin Kramer <benny.kra@googlemail.com> Wed Jul 14 22:38:02 2010 +0000
committer Benjamin Kramer <benny.kra@googlemail.com> Wed Jul 14 22:38:02 2010 +0000
tree 2cbc8f9a8ce3171d4432fc6c7f4bd686aef3b49b
parent d26e89dfcb592e2f51352640822d625ee560aca7

Don't pass StringRef by reference.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108366 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/ARM/AsmParser/ARMAsmParser.cpp

diff --git a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
index 8415d1a..4b08324 100644
--- a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -88,7 +88,7 @@
   /// its register number, or -1 if there is no match.  To allow return values
   /// to be used directly in register lists, arm registers have values between
   /// 0 and 15.
-  int MatchRegisterName(const StringRef &Name);
+  int MatchRegisterName(StringRef Name);
 
   /// }
 
@@ -97,7 +97,7 @@
   ARMAsmParser(const Target &T, MCAsmParser &_Parser)
     : TargetAsmParser(T), Parser(_Parser) {}
 
-  virtual bool ParseInstruction(const StringRef &Name, SMLoc NameLoc,
+  virtual bool ParseInstruction(StringRef Name, SMLoc NameLoc,
                                 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
 
   virtual bool ParseDirective(AsmToken DirectiveID);
@@ -517,7 +517,7 @@
   const AsmToken &Tok = Parser.getTok();
   if (Tok.isNot(AsmToken::Identifier))
     return true;
-  const StringRef &ShiftName = Tok.getString();
+  StringRef ShiftName = Tok.getString();
   if (ShiftName == "lsl" || ShiftName == "LSL")
     St = Lsl;
   else if (ShiftName == "lsr" || ShiftName == "LSR")
@@ -549,7 +549,7 @@
 }
 
 /// A hack to allow some testing, to be replaced by a real table gen version.
-int ARMAsmParser::MatchRegisterName(const StringRef &Name) {
+int ARMAsmParser::MatchRegisterName(StringRef Name) {
   if (Name == "r0" || Name == "R0")
     return 0;
   else if (Name == "r1" || Name == "R1")
@@ -593,7 +593,7 @@
                  MCInst &Inst) {
   ARMOperand &Op0 = *(ARMOperand*)Operands[0];
   assert(Op0.Kind == ARMOperand::Token && "First operand not a Token");
-  const StringRef &Mnemonic = Op0.getToken();
+  StringRef Mnemonic = Op0.getToken();
   if (Mnemonic == "add" ||
       Mnemonic == "stmfd" ||
       Mnemonic == "str" ||
@@ -658,7 +658,7 @@
 }
 
 /// Parse an arm instruction mnemonic followed by its operands.
-bool ARMAsmParser::ParseInstruction(const StringRef &Name, SMLoc NameLoc,
+bool ARMAsmParser::ParseInstruction(StringRef Name, SMLoc NameLoc,
                                SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
   OwningPtr<ARMOperand> Op;
   ARMOperand::CreateToken(Op, Name, NameLoc);
@@ -761,7 +761,7 @@
   const AsmToken &Tok = Parser.getTok();
   if (Tok.isNot(AsmToken::Identifier))
     return Error(L, "unexpected token in .syntax directive");
-  const StringRef &Mode = Tok.getString();
+  StringRef Mode = Tok.getString();
   if (Mode == "unified" || Mode == "UNIFIED")
     Parser.Lex();
   else if (Mode == "divided" || Mode == "DIVIDED")