commit 399cdca4d201f7232126c3a0643669971ede780a
author Jim Grosbach <grosbach@apple.com> Tue Oct 25 00:14:01 2011 +0000
committer Jim Grosbach <grosbach@apple.com> Tue Oct 25 00:14:01 2011 +0000
tree 56fa477b60ff2d948eea144a569b7e93827c9b4d
parent 3e6157de576e349d33a9b08d103405b3a8fb9159

ARM assembly parsing and encoding for VLD1 with writeback.

Four entry register lists.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142882 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/ARM/Disassembler/ARMDisassembler.cpp

diff --git a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
index ddc5c99..5174134 100644
--- a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
+++ b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
@@ -2078,10 +2078,14 @@
     case ARM::VLD1d32Twb_register:
     case ARM::VLD1d64Twb_fixed:
     case ARM::VLD1d64Twb_register:
-    case ARM::VLD1d8Q_UPD:
-    case ARM::VLD1d16Q_UPD:
-    case ARM::VLD1d32Q_UPD:
-    case ARM::VLD1d64Q_UPD:
+    case ARM::VLD1d8Qwb_fixed:
+    case ARM::VLD1d8Qwb_register:
+    case ARM::VLD1d16Qwb_fixed:
+    case ARM::VLD1d16Qwb_register:
+    case ARM::VLD1d32Qwb_fixed:
+    case ARM::VLD1d32Qwb_register:
+    case ARM::VLD1d64Qwb_fixed:
+    case ARM::VLD1d64Qwb_register:
     case ARM::VLD2d8_UPD:
     case ARM::VLD2d16_UPD:
     case ARM::VLD2d32_UPD: