commit 3ad5e5cf998841681e9d11e08eb82a94ddffd1f8
author Rafael Espindola <rafael.espindola@gmail.com> Wed Sep 13 12:09:43 2006 +0000
committer Rafael Espindola <rafael.espindola@gmail.com> Wed Sep 13 12:09:43 2006 +0000
tree 05fd5e609b136c6c04f3b3c5ff8e65bbb955dfae
parent c970f062e0a66d97a06eca213486a16fae1b37a4

add shifts to addressing mode 1


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30291 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/ARM/ARMInstrInfo.cpp

diff --git a/lib/Target/ARM/ARMInstrInfo.cpp b/lib/Target/ARM/ARMInstrInfo.cpp
index da1479c..810c254 100644
--- a/lib/Target/ARM/ARMInstrInfo.cpp
+++ b/lib/Target/ARM/ARMInstrInfo.cpp
@@ -33,15 +33,18 @@
                                  unsigned &SrcReg, unsigned &DstReg) const {
   MachineOpCode oc = MI.getOpcode();
   switch (oc) {
-  case ARM::MOV:
-    assert(MI.getNumOperands() == 2 &&
+  case ARM::MOV: {
+    assert(MI.getNumOperands() == 4 &&
 	   MI.getOperand(0).isRegister() &&
 	   "Invalid ARM MOV instruction");
-    if (MI.getOperand(1).isRegister()) {
+    const MachineOperand   &Arg = MI.getOperand(1);
+    const MachineOperand &Shift = MI.getOperand(2);
+    if (Arg.isRegister() && Shift.isImmediate() && Shift.getImmedValue() == 0) {
       SrcReg = MI.getOperand(1).getReg();
       DstReg = MI.getOperand(0).getReg();
       return true;
     }
   }
+  }
   return false;
 }