add patterns to the addi/addis/mulli etc instructions. Define predicates
for matching signed 16-bit and shifted 16-bit ppc immediates
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23267 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/PowerPC/PPCInstrFormats.td b/lib/Target/PowerPC/PPCInstrFormats.td
index 1475f7a..0b71daf 100644
--- a/lib/Target/PowerPC/PPCInstrFormats.td
+++ b/lib/Target/PowerPC/PPCInstrFormats.td
@@ -81,7 +81,9 @@
}
// 1.7.4 D-Form
-class DForm_base<bits<6> opcode, dag OL, string asmstr> : I<opcode, OL, asmstr>{
+class DForm_base<bits<6> opcode, dag OL, string asmstr, list<dag> pattern>
+ : I<opcode, OL, asmstr> {
+ let Pattern = pattern;
bits<5> A;
bits<5> B;
bits<16> C;
@@ -91,7 +93,8 @@
let Inst{16-31} = C;
}
-class DForm_1<bits<6> opcode, dag OL, string asmstr> : I<opcode, OL, asmstr> {
+class DForm_1<bits<6> opcode, dag OL, string asmstr>
+ : I<opcode, OL, asmstr> {
bits<5> A;
bits<16> C;
bits<5> B;
@@ -101,14 +104,16 @@
let Inst{16-31} = C;
}
-class DForm_2<bits<6> opcode, dag OL, string asmstr>
- : DForm_base<opcode, OL, asmstr>;
+class DForm_2<bits<6> opcode, dag OL, string asmstr, list<dag> pattern>
+ : DForm_base<opcode, OL, asmstr, pattern>;
-class DForm_2_r0<bits<6> opcode, dag OL, string asmstr>
+class DForm_2_r0<bits<6> opcode, dag OL, string asmstr, list<dag> pattern>
: I<opcode, OL, asmstr> {
bits<5> A;
bits<16> B;
+ let Pattern = pattern;
+
let Inst{6-10} = A;
let Inst{11-15} = 0;
let Inst{16-31} = B;