Separate decoding for STREXD and LDREXD to make each work better.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137476 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td
index fe6a27c..bfcb0f2 100644
--- a/lib/Target/ARM/ARMInstrInfo.td
+++ b/lib/Target/ARM/ARMInstrInfo.td
@@ -4082,7 +4082,7 @@
let hasExtraDefRegAllocReq = 1 in
def LDREXD: AIldrex<0b01, (outs GPR:$Rt, GPR:$Rt2),(ins addr_offset_none:$addr),
NoItinerary, "ldrexd", "\t$Rt, $Rt2, $addr", []> {
- let DecoderMethod = "DecodeDoubleRegExclusive";
+ let DecoderMethod = "DecodeDoubleRegLoad";
}
}
@@ -4099,7 +4099,7 @@
def STREXD : AIstrex<0b01, (outs GPR:$Rd),
(ins GPR:$Rt, GPR:$Rt2, addr_offset_none:$addr),
NoItinerary, "strexd", "\t$Rd, $Rt, $Rt2, $addr", []> {
- let DecoderMethod = "DecodeDoubleRegExclusive";
+ let DecoderMethod = "DecodeDoubleRegStore";
}
def CLREX : AXI<(outs), (ins), MiscFrm, NoItinerary, "clrex", []>,
diff --git a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
index 201ccf8..805cf54 100644
--- a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
+++ b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
@@ -135,9 +135,10 @@
uint64_t Address, const void *Decoder);
static bool DecodeMSRMask(llvm::MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder);
-static bool DecodeDoubleRegExclusive(llvm::MCInst &Inst, unsigned Insn,
+static bool DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder);
-
+static bool DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn,
+ uint64_t Address, const void *Decoder);
static bool DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn,
uint64_t Address, const void *Decoder);
@@ -2486,15 +2487,31 @@
return true;
}
-static bool DecodeDoubleRegExclusive(llvm::MCInst &Inst, unsigned Insn,
+static bool DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn,
+ uint64_t Address, const void *Decoder) {
+ unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
+ unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
+ unsigned pred = fieldFromInstruction32(Insn, 28, 4);
+
+ if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return false;
+
+ if (!DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)) return false;
+ if (!DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)) return false;
+ if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false;
+ if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false;
+
+ return true;
+}
+
+
+static bool DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder) {
unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
unsigned Rt = fieldFromInstruction32(Insn, 0, 4);
unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
unsigned pred = fieldFromInstruction32(Insn, 28, 4);
- if (Inst.getOpcode() == ARM::STREXD)
- if (!DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)) return false;
+ if (!DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)) return false;
if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return false;
if (Rd == Rn || Rd == Rt || Rd == Rt+1) return false;