commit 3f7aa79c2a46d525cf0468ad74ef2395246a309f
author Evan Cheng <evan.cheng@apple.com> Fri Feb 12 22:17:21 2010 +0000
committer Evan Cheng <evan.cheng@apple.com> Fri Feb 12 22:17:21 2010 +0000
tree a983400715caf051a765bbb927dc1c272bc412db
parent ee25bc294204ef326994d4142dd6bea9605e6a63

Load / store multiple instructions cannot load / store sp. Sorry, can't come up with a reasonable test case.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96023 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/ARM/ARMLoadStoreOptimizer.cpp

diff --git a/lib/Target/ARM/ARMLoadStoreOptimizer.cpp b/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
index b78b95b..4e2d181 100644
--- a/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
+++ b/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
@@ -350,7 +350,8 @@
       : ARMRegisterInfo::getRegisterNumbering(Reg);
     // AM4 - register numbers in ascending order.
     // AM5 - consecutive register numbers in ascending order.
-    if (NewOffset == Offset + (int)Size &&
+    if (Reg != ARM::SP &&
+        NewOffset == Offset + (int)Size &&
         ((isAM4 && RegNum > PRegNum) || RegNum == PRegNum+1)) {
       Offset += Size;
       PRegNum = RegNum;