| commit | 3fcbbcd7945d1216a8572ad0c543ba9c98de3723 | [log] [tgz] |
|---|---|---|
| author | Anton Korobeynikov <asl@math.spbu.ru> | Wed Oct 21 00:12:44 2009 +0000 |
| committer | Anton Korobeynikov <asl@math.spbu.ru> | Wed Oct 21 00:12:44 2009 +0000 |
| tree | eb4b11c579aecea885f1965497a22dfd6af9d1be | |
| parent | eb85a3f2fa93c04bbe6c5fae910c6cfaf1180984 [diff] [blame] |
Ignore all implicit reg operands git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84708 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/MSP430/AsmPrinter/MSP430MCInstLower.cpp b/lib/Target/MSP430/AsmPrinter/MSP430MCInstLower.cpp index e9b0c92..175b6b3 100644 --- a/lib/Target/MSP430/AsmPrinter/MSP430MCInstLower.cpp +++ b/lib/Target/MSP430/AsmPrinter/MSP430MCInstLower.cpp
@@ -100,6 +100,8 @@ MI->dump(); assert(0 && "unknown operand type"); case MachineOperand::MO_Register: + // Ignore all implicit register operands. + if (MO.isImplicit()) continue; MCOp = MCOperand::CreateReg(MO.getReg()); break; case MachineOperand::MO_Immediate: