commit 3fd0018af1b692cabfa5a002bf41f1e756aa9dde
author Hal Finkel <hfinkel@anl.gov> Mon Dec 05 17:55:17 2011 +0000
committer Hal Finkel <hfinkel@anl.gov> Mon Dec 05 17:55:17 2011 +0000
tree 7af1ee6eaa17a72254bd7860467313fa4c442ed2
parent 9489487f9863ca9f0ae9b4572d206910f1c5a581

enable PPC register scavenging by default (update tests and remove some FIXMEs)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145819 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/PowerPC/PPCFrameLowering.cpp

diff --git a/lib/Target/PowerPC/PPCFrameLowering.cpp b/lib/Target/PowerPC/PPCFrameLowering.cpp
index ec4231e..e9a4290 100644
--- a/lib/Target/PowerPC/PPCFrameLowering.cpp
+++ b/lib/Target/PowerPC/PPCFrameLowering.cpp
@@ -772,7 +772,7 @@
   // FIXME: doesn't detect whether or not we need to spill vXX, which requires
   //        r0 for now.
 
-  if (RegInfo->requiresRegisterScavenging(MF)) // FIXME (64-bit): Enable.
+  if (RegInfo->requiresRegisterScavenging(MF))
     if (needsFP(MF) || spillsCR(MF)) {
       const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
       const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;