Fix 80-column violation and extraneous brackets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146566 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/ARM/ARMFastISel.cpp b/lib/Target/ARM/ARMFastISel.cpp
index 5cb24ad..bfeac47 100644
--- a/lib/Target/ARM/ARMFastISel.cpp
+++ b/lib/Target/ARM/ARMFastISel.cpp
@@ -178,8 +178,9 @@
bool isLoadTypeLegal(Type *Ty, MVT &VT);
bool ARMEmitCmp(const Value *Src1Value, const Value *Src2Value,
bool isZExt);
- bool ARMEmitLoad(EVT VT, unsigned &ResultReg, Address &Addr, unsigned Alignment = 0,
- bool isZExt = true, bool allocReg = true);
+ bool ARMEmitLoad(EVT VT, unsigned &ResultReg, Address &Addr,
+ unsigned Alignment = 0, bool isZExt = true,
+ bool allocReg = true);
bool ARMEmitStore(EVT VT, unsigned SrcReg, Address &Addr,
unsigned Alignment = 0);
@@ -1027,11 +1028,11 @@
}
break;
case MVT::f64:
- if (Alignment && Alignment < 4) {
- // FIXME: Unaligned loads need special handling. Doublewords require
- // word-alignment.
+ // FIXME: Unaligned loads need special handling. Doublewords require
+ // word-alignment.
+ if (Alignment && Alignment < 4)
return false;
- }
+
Opc = ARM::VLDRD;
RC = TLI.getRegClassFor(VT);
break;
@@ -1145,9 +1146,9 @@
if (!Subtarget->hasVFP2()) return false;
// FIXME: Unaligned stores need special handling. Doublewords require
// word-alignment.
- if (Alignment && Alignment < 4) {
+ if (Alignment && Alignment < 4)
return false;
- }
+
StrOpc = ARM::VSTRD;
break;
}