commit 40995c93cda1e65d6b469aa06587e68e930358ff
author Evan Cheng <evan.cheng@apple.com> Thu Jul 02 23:16:11 2009 +0000
committer Evan Cheng <evan.cheng@apple.com> Thu Jul 02 23:16:11 2009 +0000
tree 4c833c3315d8859b261c22dd800ac3c25b7a8acf
parent 0ffa08fce95227126afe577963ddbd3dc15bf727

Sign extending pre/post indexed loads.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74736 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/ARM/ARMISelDAGToDAG.cpp

diff --git a/lib/Target/ARM/ARMISelDAGToDAG.cpp b/lib/Target/ARM/ARMISelDAGToDAG.cpp
index 4b73ba2..6485fc1 100644
--- a/lib/Target/ARM/ARMISelDAGToDAG.cpp
+++ b/lib/Target/ARM/ARMISelDAGToDAG.cpp
@@ -794,6 +794,7 @@
     return NULL;
 
   MVT LoadedVT = LD->getMemoryVT();
+  bool isSExtLd = LD->getExtensionType() == ISD::SEXTLOAD;
   SDValue Offset;
   bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC);
   unsigned Opcode = 0;
@@ -804,10 +805,17 @@
       Opcode = isPre ? ARM::t2LDR_PRE : ARM::t2LDR_POST;
       break;
     case MVT::i16:
-      Opcode = isPre ? ARM::t2LDRH_PRE : ARM::t2LDRH_POST;
+      if (isSExtLd)
+        Opcode = isPre ? ARM::t2LDRSH_PRE : ARM::t2LDRSH_POST;
+      else
+        Opcode = isPre ? ARM::t2LDRH_PRE : ARM::t2LDRH_POST;
       break;
     case MVT::i8:
-      Opcode = isPre ? ARM::t2LDRB_PRE : ARM::t2LDRB_POST;
+    case MVT::i1:
+      if (isSExtLd)
+        Opcode = isPre ? ARM::t2LDRSB_PRE : ARM::t2LDRSB_POST;
+      else
+        Opcode = isPre ? ARM::t2LDRB_PRE : ARM::t2LDRB_POST;
       break;
     default:
       return NULL;