MC machine encoding for simple aritmetic instructions that use a shifted
register operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116259 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/ARM/ARMMCCodeEmitter.cpp b/lib/Target/ARM/ARMMCCodeEmitter.cpp
index fce1f39..ad87b38 100644
--- a/lib/Target/ARM/ARMMCCodeEmitter.cpp
+++ b/lib/Target/ARM/ARMMCCodeEmitter.cpp
@@ -13,6 +13,7 @@
#define DEBUG_TYPE "arm-emitter"
#include "ARM.h"
+#include "ARMAddressingModes.h"
#include "ARMInstrInfo.h"
#include "llvm/MC/MCCodeEmitter.h"
#include "llvm/MC/MCExpr.h"
@@ -139,8 +140,27 @@
return;
++MCNumEmitted; // Keep track of the # of mi's emitted
+ // FIXME: TableGen doesn't deal well with operands that expand to multiple
+ // machine instruction operands, so for now we'll fix those up here.
switch (Opcode) {
- //FIXME: Any non-pseudos that need special handling, if there are any...
+ case ARM::ADDrs:
+ case ARM::ANDrs:
+ case ARM::BICrs:
+ case ARM::EORrs:
+ case ARM::ORRrs:
+ case ARM::SUBrs: {
+ // The so_reg operand needs the shift ammount encoded.
+ unsigned Value = getBinaryCodeForInstr(MI);
+ unsigned ShVal = MI.getOperand(4).getImm();
+ unsigned ShType = ARM_AM::getShiftOpcEncoding(ARM_AM::getSORegShOp(ShVal));
+ unsigned ShAmt = ARM_AM::getSORegOffset(ShVal);
+
+ Value |= ShType << ARMII::ShiftTypeShift;
+ Value |= ShAmt << ARMII::ShiftShift;
+
+ EmitConstant(Value, 4, CurByte, OS);
+ break;
+ }
default: {
unsigned Value = getBinaryCodeForInstr(MI);
EmitConstant(Value, 4, CurByte, OS);