commit 4334e032525d6c9038605f3871b945e8cbe6fab7
author Jim Grosbach <grosbach@apple.com> Mon Oct 31 21:50:31 2011 +0000
committer Jim Grosbach <grosbach@apple.com> Mon Oct 31 21:50:31 2011 +0000
tree 0c6218d6f958eb65c5bef4708000ae7de07f8ea0
parent 0ba11795eec4e63cbb01890fea6888ba4f4498d8

ARM VST1 w/ writeback assembly parsing and encoding.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143369 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/ARM/Disassembler/ARMDisassembler.cpp

diff --git a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
index 8870024..e81cc76 100644
--- a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
+++ b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
@@ -2183,14 +2183,22 @@
 
   // Writeback Operand
   switch (Inst.getOpcode()) {
-    case ARM::VST1d8_UPD:
-    case ARM::VST1d16_UPD:
-    case ARM::VST1d32_UPD:
-    case ARM::VST1d64_UPD:
-    case ARM::VST1q8_UPD:
-    case ARM::VST1q16_UPD:
-    case ARM::VST1q32_UPD:
-    case ARM::VST1q64_UPD:
+    case ARM::VST1d8wb_fixed:
+    case ARM::VST1d16wb_fixed:
+    case ARM::VST1d32wb_fixed:
+    case ARM::VST1d64wb_fixed:
+    case ARM::VST1d8wb_register:
+    case ARM::VST1d16wb_register:
+    case ARM::VST1d32wb_register:
+    case ARM::VST1d64wb_register:
+    case ARM::VST1q8wb_fixed:
+    case ARM::VST1q16wb_fixed:
+    case ARM::VST1q32wb_fixed:
+    case ARM::VST1q64wb_fixed:
+    case ARM::VST1q8wb_register:
+    case ARM::VST1q16wb_register:
+    case ARM::VST1q32wb_register:
+    case ARM::VST1q64wb_register:
     case ARM::VST1d8T_UPD:
     case ARM::VST1d16T_UPD:
     case ARM::VST1d32T_UPD:
@@ -2249,10 +2257,6 @@
     case ARM::VST1q16:
     case ARM::VST1q32:
     case ARM::VST1q64:
-    case ARM::VST1q8_UPD:
-    case ARM::VST1q16_UPD:
-    case ARM::VST1q32_UPD:
-    case ARM::VST1q64_UPD:
     case ARM::VST1d8T:
     case ARM::VST1d16T:
     case ARM::VST1d32T: