another solution to the fsel issue. Instead of having 4 variants, just force
the comparison to be 64-bits. This is fine because extensions from float
to double are free.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23589 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
index 3a92d08..14c7406 100644
--- a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
+++ b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
@@ -753,18 +753,14 @@
return SDOperand(Result.Val, Op.ResNo);
}
case PPCISD::FSEL: {
- unsigned Opc;
- if (N->getValueType(0) == MVT::f32) {
- Opc = N->getOperand(0).getValueType() == MVT::f32 ?
- PPC::FSELSS : PPC::FSELSD;
- } else {
- Opc = N->getOperand(0).getValueType() == MVT::f64 ?
- PPC::FSELDD : PPC::FSELDS;
- }
- CurDAG->SelectNodeTo(N, Opc, N->getValueType(0),
- Select(N->getOperand(0)),
- Select(N->getOperand(1)),
- Select(N->getOperand(2)));
+ SDOperand Comparison = Select(N->getOperand(0));
+ // Extend the comparison to 64-bits.
+ if (Comparison.getValueType() == MVT::f32)
+ Comparison = CurDAG->getTargetNode(PPC::FMRSD, MVT::f64, Comparison);
+
+ unsigned Opc = N->getValueType(0) == MVT::f32 ? PPC::FSELS : PPC::FSELD;
+ CurDAG->SelectNodeTo(N, Opc, N->getValueType(0), Comparison,
+ Select(N->getOperand(1)), Select(N->getOperand(2)));
return SDOperand(N, 0);
}
case PPCISD::FCFID: