Change the post-RA scheduler to iterate through the
basic-block segments bottom-up instead of top down. This
is the first step in a general restructuring of the way
register liveness is tracked in the post-RA scheduler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63643 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/CodeGen/PostRASchedulerList.cpp b/lib/CodeGen/PostRASchedulerList.cpp
index 7bf3b3c..0cb3b03 100644
--- a/lib/CodeGen/PostRASchedulerList.cpp
+++ b/lib/CodeGen/PostRASchedulerList.cpp
@@ -189,15 +189,17 @@
MBB != MBBe; ++MBB) {
// Schedule each sequence of instructions not interrupted by a label
// or anything else that effectively needs to shut down scheduling.
- MachineBasicBlock::iterator Current = MBB->begin(), End = MBB->end();
- for (MachineBasicBlock::iterator MI = Current; MI != End; ++MI)
+ MachineBasicBlock::iterator Current = MBB->end(), Top = MBB->begin();
+ for (MachineBasicBlock::iterator I = Current; I != Top; ) {
+ MachineInstr *MI = --I;
if (MI->getDesc().isTerminator() || MI->isLabel()) {
- Scheduler.Run(0, MBB, Current, MI);
+ Scheduler.Run(0, MBB, next(I), Current);
Scheduler.EmitSchedule();
- Current = next(MI);
+ Current = I;
}
+ }
- Scheduler.Run(0, MBB, Current, End);
+ Scheduler.Run(0, MBB, Top, Current);
Scheduler.EmitSchedule();
}
@@ -415,10 +417,10 @@
// instructions from the bottom up, tracking information about liveness
// as we go to help determine which registers are available.
bool Changed = false;
- unsigned Count = BB->size() - 1;
- for (MachineBasicBlock::reverse_iterator I = BB->rbegin(), E = BB->rend();
- I != E; ++I, --Count) {
- MachineInstr *MI = &*I;
+ unsigned Count = SUnits.size() - 1;
+ for (MachineBasicBlock::iterator I = End, E = Begin;
+ I != E; --Count) {
+ MachineInstr *MI = --I;
// After regalloc, IMPLICIT_DEF instructions aren't safe to treat as
// dependence-breaking. In the case of an INSERT_SUBREG, the IMPLICIT_DEF