commit 451afbc6a22a3a662eea7e86088c65c36e84949f
author Chad Rosier <mcrosier@apple.com> Fri Nov 04 23:45:39 2011 +0000
committer Chad Rosier <mcrosier@apple.com> Fri Nov 04 23:45:39 2011 +0000
tree ac96170a0f649ccf752eea3a49b90c60bd5305b2
parent 774ec45f3d7ef8b6fafe8d653ccaae0fd0a1933e

Cannot create a result register for non-legal types.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143749 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/ARM/ARMFastISel.cpp

diff --git a/lib/Target/ARM/ARMFastISel.cpp b/lib/Target/ARM/ARMFastISel.cpp
index a315c30..517f73f 100644
--- a/lib/Target/ARM/ARMFastISel.cpp
+++ b/lib/Target/ARM/ARMFastISel.cpp
@@ -552,8 +552,9 @@
   // do so now.
   const ConstantInt *CI = cast<ConstantInt>(C);
   if (Subtarget->hasV6T2Ops() && isUInt<16>(CI->getZExtValue())) {
+    EVT SrcVT = MVT::i32;
     unsigned Opc = isThumb ? ARM::t2MOVi16 : ARM::MOVi16;
-    unsigned ImmReg = createResultReg(TLI.getRegClassFor(VT));
+    unsigned ImmReg = createResultReg(TLI.getRegClassFor(SrcVT));
     AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
                             TII.get(Opc), ImmReg)
                     .addImm(CI->getSExtValue()));