ARM rot_imm printing adjustment.
Allow the rot_imm operand to be optional. This sets the stage for refactoring
away the "rr" versions from the multiclasses and replacing them with Pat<>s.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136154 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td
index 3b75593..70c55e7 100644
--- a/lib/Target/ARM/ARMInstrInfo.td
+++ b/lib/Target/ARM/ARMInstrInfo.td
@@ -999,7 +999,7 @@
let Inst{3-0} = Rm;
}
def r_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm, rot_imm:$rot),
- IIC_iEXTr, opc, "\t$Rd, $Rm, $rot",
+ IIC_iEXTr, opc, "\t$Rd, $Rm$rot",
[(set GPR:$Rd, (opnode (rotr GPR:$Rm, rot_imm:$rot)))]>,
Requires<[IsARM, HasV6]> {
bits<4> Rd;
@@ -1021,7 +1021,7 @@
let Inst{11-10} = 0b00;
}
def r_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm, rot_imm:$rot),
- IIC_iEXTr, opc, "\t$Rd, $Rm, $rot",
+ IIC_iEXTr, opc, "\t$Rd, $Rm$rot",
[/* For disassembly only; pattern left blank */]>,
Requires<[IsARM, HasV6]> {
bits<2> rot;
@@ -1048,7 +1048,7 @@
}
def rr_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm,
rot_imm:$rot),
- IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm, $rot",
+ IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot",
[(set GPR:$Rd, (opnode GPR:$Rn,
(rotr GPR:$Rm, rot_imm:$rot)))]>,
Requires<[IsARM, HasV6]> {
@@ -1074,7 +1074,7 @@
}
def rr_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm,
rot_imm:$rot),
- IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm, $rot",
+ IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot",
[/* For disassembly only; pattern left blank */]>,
Requires<[IsARM, HasV6]> {
bits<4> Rn;
diff --git a/lib/Target/ARM/ARMInstrThumb2.td b/lib/Target/ARM/ARMInstrThumb2.td
index bc9d878..eb0fd01 100644
--- a/lib/Target/ARM/ARMInstrThumb2.td
+++ b/lib/Target/ARM/ARMInstrThumb2.td
@@ -990,7 +990,7 @@
let Inst{5-4} = 0b00; // rotate
}
def r_rot : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm, rot_imm:$rot), IIC_iEXTr,
- opc, ".w\t$Rd, $Rm, $rot",
+ opc, ".w\t$Rd, $Rm$rot",
[(set rGPR:$Rd, (opnode (rotr rGPR:$Rm, rot_imm:$rot)))]> {
let Inst{31-27} = 0b11111;
let Inst{26-23} = 0b0100;
@@ -1019,7 +1019,7 @@
let Inst{5-4} = 0b00; // rotate
}
def r_rot : T2TwoReg<(outs rGPR:$dst), (ins rGPR:$Rm, rot_imm:$rot),
- IIC_iEXTr, opc, "\t$dst, $Rm, $rot",
+ IIC_iEXTr, opc, "\t$dst, $Rm$rot",
[(set rGPR:$dst, (opnode (rotr rGPR:$Rm, rot_imm:$rot)))]>,
Requires<[HasT2ExtractPack, IsThumb2]> {
let Inst{31-27} = 0b11111;
@@ -1079,7 +1079,7 @@
}
def rr_rot : T2ThreeReg<(outs rGPR:$Rd),
(ins rGPR:$Rn, rGPR:$Rm, rot_imm:$rot),
- IIC_iEXTAsr, opc, "\t$Rd, $Rn, $Rm, $rot",
+ IIC_iEXTAsr, opc, "\t$Rd, $Rn, $Rm$rot",
[(set rGPR:$Rd, (opnode rGPR:$Rn,
(rotr rGPR:$Rm, rot_imm:$rot)))]>,
Requires<[HasT2ExtractPack, IsThumb2]> {
@@ -1105,7 +1105,7 @@
let Inst{5-4} = 0b00; // rotate
}
def rr_rot :T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm,rot_imm:$rot),
- IIC_iEXTAsr, opc, "\t$Rd, $Rn, $Rm, $rot", []> {
+ IIC_iEXTAsr, opc, "\t$Rd, $Rn, $Rm$rot", []> {
let Inst{31-27} = 0b11111;
let Inst{26-23} = 0b0100;
let Inst{22-20} = opcod;
diff --git a/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp b/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
index 30ec498..fe8459e 100644
--- a/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
+++ b/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
@@ -841,7 +841,7 @@
unsigned Imm = MI->getOperand(OpNum).getImm();
if (Imm == 0)
return;
- O << "ror #";
+ O << ", ror #";
switch (Imm) {
default: assert (0 && "illegal ror immediate!");
case 1: O << "8\n"; break;