Fix fall outs from my recent change on how carry bit is modeled during isel.
Now the 'S' instructions, e.g. ADDS, treat S bit as optional operand as well.
Also fix isel hook to correctly set the optional operand.
rdar://10073745
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139157 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp
index 0756be3..64ceac4 100644
--- a/lib/Target/ARM/ARMISelLowering.cpp
+++ b/lib/Target/ARM/ARMISelLowering.cpp
@@ -5708,7 +5708,7 @@
// the optional operand to CPSR. Otherwise, remove the CPSR implicit def.
const MCInstrDesc &MCID = MI->getDesc();
if (Node->hasAnyUseOfValue(1)) {
- MachineOperand &MO = MI->getOperand(MCID.getNumOperands() - 2);
+ MachineOperand &MO = MI->getOperand(MCID.getNumOperands() - 1);
MO.setReg(ARM::CPSR);
MO.setIsDef(true);
} else {