commit 4cce6b4c7882ef0cc993d931b90bf33985c96110
author Evan Cheng <evan.cheng@apple.com> Fri Apr 11 17:53:36 2008 +0000
committer Evan Cheng <evan.cheng@apple.com> Fri Apr 11 17:53:36 2008 +0000
tree ae568a7364fb4567178847ebd911b4c94ae62a42
parent 6b893fced8ce8ac711d4fd6718f56c921ad8a6e3

Use of implicit_def is not part of live interval. Create empty intervals for the uses when the live interval is being spilled.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49542 91177308-0d34-0410-b5e6-96231b3b80d8

lib/CodeGen/LiveIntervalAnalysis.cpp

diff --git a/lib/CodeGen/LiveIntervalAnalysis.cpp b/lib/CodeGen/LiveIntervalAnalysis.cpp
index 0556f79..9f72035 100644
--- a/lib/CodeGen/LiveIntervalAnalysis.cpp
+++ b/lib/CodeGen/LiveIntervalAnalysis.cpp
@@ -1319,19 +1319,37 @@
       Restores[i].index = -1;
 }
 
-/// removeSpilledImpDefs - Remove IMPLICIT_DEF instructions which are being
-/// spilled.
-void LiveIntervals::removeSpilledImpDefs(const LiveInterval &li,
-                                         VirtRegMap &vrm) {
+/// handleSpilledImpDefs - Remove IMPLICIT_DEF instructions which are being
+/// spilled and create empty intervals for their uses.
+void
+LiveIntervals::handleSpilledImpDefs(const LiveInterval &li, VirtRegMap &vrm,
+                                    const TargetRegisterClass* rc,
+                                    std::vector<LiveInterval*> &NewLIs) {
   for (MachineRegisterInfo::reg_iterator ri = mri_->reg_begin(li.reg),
          re = mri_->reg_end(); ri != re; ) {
+    MachineOperand &O = ri.getOperand();
     MachineInstr *MI = &*ri;
     ++ri;
-    if (MI->getOpcode() != TargetInstrInfo::IMPLICIT_DEF)
-      continue;
-    RemoveMachineInstrFromMaps(MI);
-    vrm.RemoveMachineInstrFromMaps(MI);
-    MI->eraseFromParent();
+    if (O.isDef()) {
+      assert(MI->getOpcode() == TargetInstrInfo::IMPLICIT_DEF &&
+             "Register def was not rewritten?");
+      RemoveMachineInstrFromMaps(MI);
+      vrm.RemoveMachineInstrFromMaps(MI);
+      MI->eraseFromParent();
+    } else {
+      // This must be an use of an implicit_def so it's not part of the live
+      // interval. Create a new empty live interval for it.
+      // FIXME: Can we simply erase some of the instructions? e.g. Stores?
+      unsigned NewVReg = mri_->createVirtualRegister(rc);
+      vrm.grow();
+      vrm.setIsImplicitlyDefined(NewVReg);
+      NewLIs.push_back(&getOrCreateInterval(NewVReg));
+      for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
+        MachineOperand &MO = MI->getOperand(i);
+        if (MO.isReg() && MO.getReg() == li.reg)
+          MO.setReg(NewVReg);
+      }
+    }
   }
 }
 
@@ -1415,7 +1433,7 @@
       IsFirstRange = false;
     }
 
-    removeSpilledImpDefs(li, vrm);
+    handleSpilledImpDefs(li, vrm, rc, NewLIs);
     return NewLIs;
   }
 
@@ -1485,7 +1503,7 @@
 
   // Insert spills / restores if we are splitting.
   if (!TrySplit) {
-    removeSpilledImpDefs(li, vrm);
+    handleSpilledImpDefs(li, vrm, rc, NewLIs);
     return NewLIs;
   }
 
@@ -1640,7 +1658,7 @@
     }
   }
 
-  removeSpilledImpDefs(li, vrm);
+  handleSpilledImpDefs(li, vrm, rc, RetNewLIs);
   return RetNewLIs;
 }