ARM more NEON VLD/VST composite physical register refactoring.
Register pair, all lanes subscripting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152157 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
index fcb8544..fe93a4c 100644
--- a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -1101,11 +1101,6 @@
return VectorList.Count == 4;
}
- bool isVecListTwoQ() const {
- if (!isDoubleSpacedVectorList()) return false;
- return VectorList.Count == 2;
- }
-
bool isVecListDPairSpaced() const {
if (!isSingleSpacedVectorList()) return false;
return (ARMMCRegisterClasses[ARM::DPairSpcRegClassID]
@@ -1139,7 +1134,7 @@
.contains(VectorList.RegNum));
}
- bool isVecListTwoQAllLanes() const {
+ bool isVecListDPairSpacedAllLanes() const {
if (!isDoubleSpacedVectorAllLanes()) return false;
return VectorList.Count == 2;
}
@@ -3169,8 +3164,10 @@
case AllLanes:
// Two-register operands have been converted to the
// composite register classes.
- if (Count == 2 && Spacing == 1) {
- const MCRegisterClass *RC = &ARMMCRegisterClasses[ARM::DPairRegClassID];
+ if (Count == 2) {
+ const MCRegisterClass *RC = (Spacing == 1) ?
+ &ARMMCRegisterClasses[ARM::DPairRegClassID] :
+ &ARMMCRegisterClasses[ARM::DPairSpcRegClassID];
FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC);
}
Operands.push_back(ARMOperand::CreateVectorListAllLanes(FirstReg, Count,