commit 507a58ac9b20ddcea2e56a014be26b8f8cc0ecb8
author Andrew Lenharth <andrewl@lenharth.org> Sat Jun 14 05:48:15 2008 +0000
committer Andrew Lenharth <andrewl@lenharth.org> Sat Jun 14 05:48:15 2008 +0000
tree 53d5d29cee43a7eb314904ce4ada56e735f3efea
parent c5dc660ea0b153904de601eadd40fa4962c8c71c

add missing atomic intrinsic from gcc

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52270 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/X86/X86ISelLowering.cpp

diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index 53f42b9..11442b5 100644
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -5963,7 +5963,8 @@
 X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr,
                                                        MachineBasicBlock *MBB,
                                                        unsigned regOpc,
-                                                       unsigned immOpc) {
+                                                       unsigned immOpc,
+                                                       bool invSrc) {
   // For the atomic bitwise operator, we generate
   //   thisMBB:
   //   newMBB:
@@ -6012,7 +6013,14 @@
   MachineInstrBuilder MIB = BuildMI(newMBB, TII->get(X86::MOV32rm), t1);
   for (int i=0; i <= lastAddrIndx; ++i)
     (*MIB).addOperand(*argOpers[i]);
-  
+
+  unsigned tt = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
+  if (invSrc) {
+    MIB = BuildMI(newMBB, TII->get(X86::NOT32r), tt).addReg(t1);
+  }
+  else 
+    tt = t1;
+
   unsigned t2 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
   assert(   (argOpers[valArgIndx]->isReg() || argOpers[valArgIndx]->isImm())
          && "invalid operand");
@@ -6020,9 +6028,9 @@
     MIB = BuildMI(newMBB, TII->get(regOpc), t2);
   else
     MIB = BuildMI(newMBB, TII->get(immOpc), t2);
-  MIB.addReg(t1);
+  MIB.addReg(tt);
   (*MIB).addOperand(*argOpers[valArgIndx]);
-  
+
   MIB = BuildMI(newMBB, TII->get(X86::MOV32rr), X86::EAX);
   MIB.addReg(t1);
   
@@ -6286,6 +6294,9 @@
   case X86::ATOMXOR32:
     return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR32rr,
                                                        X86::XOR32ri);
+  case X86::ATOMNAND32:
+    return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
+                                               X86::AND32ri, true);
   case X86::ATOMMIN32:
     return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL32rr);
   case X86::ATOMMAX32: