commit 5126984b1da4bda0e93961da07e883699f1f2d57
author Chris Lattner <sabre@nondot.org> Wed Mar 01 05:50:56 2006 +0000
committer Chris Lattner <sabre@nondot.org> Wed Mar 01 05:50:56 2006 +0000
tree 282a6a6e3778ffa0bee4990b791b8b0236a2b484
parent c607fa8665942710d0748184bf99a3051dfda3d8

Compile this:

void foo(float a, int *b) { *b = a; }

to this:

_foo:
        fctiwz f0, f1
        stfiwx f0, 0, r4
        blr

instead of this:

_foo:
        fctiwz f0, f1
        stfd f0, -8(r1)
        lwz r2, -4(r1)
        stw r2, 0(r4)
        blr

This implements CodeGen/PowerPC/stfiwx.ll, and also incidentally does the
right thing for GCC bugzilla 26505.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26447 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/PowerPC/PPCISelLowering.cpp

diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp
index 4009522..c94b9f1 100644
--- a/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -187,6 +187,7 @@
   
   // We have target-specific dag combine patterns for the following nodes:
   setTargetDAGCombine(ISD::SINT_TO_FP);
+  setTargetDAGCombine(ISD::STORE);
   
   computeRegisterProperties();
 }
@@ -198,6 +199,7 @@
   case PPCISD::FCFID:         return "PPCISD::FCFID";
   case PPCISD::FCTIDZ:        return "PPCISD::FCTIDZ";
   case PPCISD::FCTIWZ:        return "PPCISD::FCTIWZ";
+  case PPCISD::STFIWX:        return "PPCISD::STFIWX";
   case PPCISD::VMADDFP:       return "PPCISD::VMADDFP";
   case PPCISD::VNMSUBFP:      return "PPCISD::VNMSUBFP";
   case PPCISD::Hi:            return "PPCISD::Hi";
@@ -1032,6 +1034,25 @@
       }
     }
     break;
+  case ISD::STORE:
+    // Turn STORE (FP_TO_SINT F) -> STFIWX(FCTIWZ(F)).
+    if (TM.getSubtarget<PPCSubtarget>().hasSTFIWX() &&
+        N->getOperand(1).getOpcode() == ISD::FP_TO_SINT &&
+        N->getOperand(1).getValueType() == MVT::i32) {
+      SDOperand Val = N->getOperand(1).getOperand(0);
+      if (Val.getValueType() == MVT::f32) {
+        Val = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Val);
+        DCI.AddToWorklist(Val.Val);
+      }
+      Val = DAG.getNode(PPCISD::FCTIWZ, MVT::f64, Val);
+      DCI.AddToWorklist(Val.Val);
+
+      Val = DAG.getNode(PPCISD::STFIWX, MVT::Other, N->getOperand(0), Val,
+                        N->getOperand(2), N->getOperand(3));
+      DCI.AddToWorklist(Val.Val);
+      return Val;
+    }
+    break;
   }
   
   return SDOperand();