commit 519020adf1cf57e2e93cc4fd49c385c47f7ff0f7
author Owen Anderson <resistor@mac.com> Wed Sep 21 17:58:45 2011 +0000
committer Owen Anderson <resistor@mac.com> Wed Sep 21 17:58:45 2011 +0000
tree 1a95cafe419caed38ed9d05d88504b0ee1a3235c
parent 4d77ae61f179819a3e5021790755ab4d640a00f5

These do not need to be conditional on the presence of CommentStream, as they have a fallback path now.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140267 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp

diff --git a/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp b/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
index 277d44c..16bb25a 100644
--- a/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
+++ b/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
@@ -72,7 +72,7 @@
 
     O << ", " << getRegisterName(MO2.getReg());
     assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
-    if (CommentStream) printAnnotation(O, Annot);
+    printAnnotation(O, Annot);
     return;
   }
 
@@ -90,12 +90,12 @@
       << ", " << getRegisterName(MO1.getReg());
 
     if (ARM_AM::getSORegShOp(MO2.getImm()) == ARM_AM::rrx) {
-      if (CommentStream) printAnnotation(O, Annot);
+      printAnnotation(O, Annot);
       return;
     }
 
     O << ", #" << translateShiftImm(ARM_AM::getSORegOffset(MO2.getImm()));
-    if (CommentStream) printAnnotation(O, Annot);
+    printAnnotation(O, Annot);
     return;
   }
 
@@ -109,7 +109,7 @@
       O << ".w";
     O << '\t';
     printRegisterList(MI, 4, O);
-    if (CommentStream) printAnnotation(O, Annot);
+    printAnnotation(O, Annot);
     return;
   }
   if (Opcode == ARM::STR_PRE_IMM && MI->getOperand(2).getReg() == ARM::SP &&
@@ -117,7 +117,7 @@
     O << '\t' << "push";
     printPredicateOperand(MI, 4, O);
     O << "\t{" << getRegisterName(MI->getOperand(1).getReg()) << "}";
-    if (CommentStream) printAnnotation(O, Annot);
+    printAnnotation(O, Annot);
     return;
   }
 
@@ -130,7 +130,7 @@
       O << ".w";
     O << '\t';
     printRegisterList(MI, 4, O);
-    if (CommentStream) printAnnotation(O, Annot);
+    printAnnotation(O, Annot);
     return;
   }
   if (Opcode == ARM::LDR_POST_IMM && MI->getOperand(2).getReg() == ARM::SP &&
@@ -138,7 +138,7 @@
     O << '\t' << "pop";
     printPredicateOperand(MI, 5, O);
     O << "\t{" << getRegisterName(MI->getOperand(0).getReg()) << "}";
-    if (CommentStream) printAnnotation(O, Annot);
+    printAnnotation(O, Annot);
     return;
   }
 
@@ -150,7 +150,7 @@
     printPredicateOperand(MI, 2, O);
     O << '\t';
     printRegisterList(MI, 4, O);
-    if (CommentStream) printAnnotation(O, Annot);
+    printAnnotation(O, Annot);
     return;
   }
 
@@ -161,7 +161,7 @@
     printPredicateOperand(MI, 2, O);
     O << '\t';
     printRegisterList(MI, 4, O);
-    if (CommentStream) printAnnotation(O, Annot);
+    printAnnotation(O, Annot);
     return;
   }
 
@@ -180,7 +180,7 @@
     if (Writeback) O << "!";
     O << ", ";
     printRegisterList(MI, 3, O);
-    if (CommentStream) printAnnotation(O, Annot);
+    printAnnotation(O, Annot);
     return;
   }
 
@@ -189,12 +189,12 @@
       MI->getOperand(1).getReg() == ARM::R8) {
     O << "\tnop";
     printPredicateOperand(MI, 2, O);
-    if (CommentStream) printAnnotation(O, Annot);
+    printAnnotation(O, Annot);
     return;
   }
 
   printInstruction(MI, O);
-  if (CommentStream) printAnnotation(O, Annot);
+  printAnnotation(O, Annot);
 }
 
 void ARMInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,