Added InstrSchedClass to each of the PowerPC Instructions.
Note that when adding new instructions that you should refer to the table at the
bottom of PPCSchedule.td.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23830 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/Target.td b/lib/Target/Target.td
index 994a71d..f592fce 100644
--- a/lib/Target/Target.td
+++ b/lib/Target/Target.td
@@ -113,6 +113,12 @@
//===----------------------------------------------------------------------===//
+// Pull in the common support for scheduling
+//
+include "../TargetSchedule.td"
+
+
+//===----------------------------------------------------------------------===//
// Instruction set description - These classes correspond to the C++ classes in
// the Target/TargetInstrInfo.h file.
//
@@ -147,6 +153,8 @@
bit isTerminator = 0; // Is this part of the terminator for a basic block?
bit hasDelaySlot = 0; // Does this instruction have an delay slot?
bit usesCustomDAGSchedInserter = 0; // Pseudo instr needing special help.
+
+ InstrItinClass Itinerary; // Execution steps used for scheduling.
}
@@ -242,11 +250,6 @@
}
//===----------------------------------------------------------------------===//
-// Pull in the common support for scheduling
-//
-include "../TargetSchedule.td"
-
-//===----------------------------------------------------------------------===//
// SubtargetFeature - A characteristic of the chip set.
//
class SubtargetFeature<string n, string d> {