Allow explicit %reg0 operands beyond what the .td file describes.
ARM uses these to indicate predicates.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91922 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/CodeGen/MachineVerifier.cpp b/lib/CodeGen/MachineVerifier.cpp
index 917d053..959269f 100644
--- a/lib/CodeGen/MachineVerifier.cpp
+++ b/lib/CodeGen/MachineVerifier.cpp
@@ -553,7 +553,8 @@
report("Explicit operand marked as implicit", MO, MONum);
}
} else {
- if (MO->isReg() && !MO->isImplicit() && !TI.isVariadic())
+ // ARM adds %reg0 operands to indicate predicates. We'll allow that.
+ if (MO->isReg() && !MO->isImplicit() && !TI.isVariadic() && MO->getReg())
report("Extra explicit operand on non-variadic instruction", MO, MONum);
}