commit 588bbbffa1cf29201c72b8b3f04c6330f4bde2dd
author Chris Lattner <sabre@nondot.org> Thu Apr 21 06:28:15 2005 +0000
committer Chris Lattner <sabre@nondot.org> Thu Apr 21 06:28:15 2005 +0000
tree 409c6931f1e1972962f4df6969f2af340b2a1f47
parent 1c2a9b95dc73c6fd11052e384ea5b10d011abb66

Improve and elimination.  On PPC, for:

bool %test(int %X) {
        %Y = and int %X, 8
        %Z = setne int %Y, 0
        ret bool %Z
}

we now generate this:

        rlwinm r2, r3, 0, 28, 28
        srwi r3, r2, 3

instead of this:

        rlwinm r2, r3, 0, 28, 28
        srwi r2, r2, 3
        rlwinm r3, r2, 0, 31, 31

I'll leave it to Nate to get it down to one instruction. :)

---------------------------------------------------------------------


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21391 91177308-0d34-0410-b5e6-96231b3b80d8

lib/CodeGen/SelectionDAG/SelectionDAG.cpp

diff --git a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index b82d102..0bfd578 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -781,7 +781,7 @@
 
   case ISD::AND:
     // (X & C1) & C2 == 0   iff   C1 & C2 == 0.
-    if (ConstantSDNode *AndRHS = dyn_cast<ConstantSDNode>(Op.getOperand(0)))
+    if (ConstantSDNode *AndRHS = dyn_cast<ConstantSDNode>(Op.getOperand(1)))
       return MaskedValueIsZero(Op.getOperand(0),AndRHS->getValue() & Mask, TLI);
 
     // FALL THROUGH
@@ -792,9 +792,23 @@
   case ISD::SELECT:
     return MaskedValueIsZero(Op.getOperand(1), Mask, TLI) &&
            MaskedValueIsZero(Op.getOperand(2), Mask, TLI);
-    
-  // TODO: (shl X, C1) & C2 == 0   iff  (-1 << C1) & C2 == 0
-  // TODO: (ushr X, C1) & C2 == 0   iff  (-1 >> C1) & C2 == 0
+
+  case ISD::SRL:
+    // (ushr X, C1) & C2 == 0   iff  X & (C2 << C1) == 0
+    if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
+      uint64_t NewVal = Mask << ShAmt->getValue();
+      SrcBits = MVT::getSizeInBits(Op.getValueType());
+      if (SrcBits != 64) NewVal &= (1ULL << SrcBits)-1;
+      return MaskedValueIsZero(Op.getOperand(0), NewVal, TLI);
+    }
+    return false;
+  case ISD::SHL:
+    // (ushl X, C1) & C2 == 0   iff  X & (C2 >> C1) == 0
+    if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
+      uint64_t NewVal = Mask >> ShAmt->getValue();
+      return MaskedValueIsZero(Op.getOperand(0), NewVal, TLI);
+    }
+    return false;
   default: break;
   }
 
@@ -941,8 +955,14 @@
       if (MaskedValueIsZero(N1, C2, TLI))  // X and 0 -> 0
         return getConstant(0, VT);
 
-      if (MaskedValueIsZero(N1, ~C2, TLI))
-        return N1;                // if (X & ~C2) -> 0, the and is redundant
+      {
+        uint64_t NotC2 = ~C2;
+        if (VT != MVT::i64)
+          NotC2 &= (1ULL << MVT::getSizeInBits(VT))-1;
+
+        if (MaskedValueIsZero(N1, NotC2, TLI))
+          return N1;                // if (X & ~C2) -> 0, the and is redundant
+      }
 
       // FIXME: Should add a corresponding version of this for
       // ZERO_EXTEND/SIGN_EXTEND by converting them to an ANY_EXTEND node which