commit 5921675ff5ea632ab1e6d7aa5d1f263b858bbafa
author Jim Grosbach <grosbach@apple.com> Mon Oct 24 23:26:05 2011 +0000
committer Jim Grosbach <grosbach@apple.com> Mon Oct 24 23:26:05 2011 +0000
tree c95a5cf4a756419e6151de09ede3573882d3f8a0
parent d8fa76d4bed067cd8662c3196211bc90cc8d4470

ARM assembly parsing and encoding for VLD1 w/ writeback.

Three entry register list variation.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142876 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/ARM/Disassembler/ARMDisassembler.cpp

diff --git a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
index d6b9260..ddc5c99 100644
--- a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
+++ b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
@@ -2070,10 +2070,14 @@
     case ARM::VLD1q16wb_register:
     case ARM::VLD1q32wb_register:
     case ARM::VLD1q64wb_register:
-    case ARM::VLD1d8T_UPD:
-    case ARM::VLD1d16T_UPD:
-    case ARM::VLD1d32T_UPD:
-    case ARM::VLD1d64T_UPD:
+    case ARM::VLD1d8Twb_fixed:
+    case ARM::VLD1d8Twb_register:
+    case ARM::VLD1d16Twb_fixed:
+    case ARM::VLD1d16Twb_register:
+    case ARM::VLD1d32Twb_fixed:
+    case ARM::VLD1d32Twb_register:
+    case ARM::VLD1d64Twb_fixed:
+    case ARM::VLD1d64Twb_register:
     case ARM::VLD1d8Q_UPD:
     case ARM::VLD1d16Q_UPD:
     case ARM::VLD1d32Q_UPD: