commit 5960e4eb68be6b3bca6369f6a95d7de5ed8a9ead
author Evan Cheng <evan.cheng@apple.com> Mon Sep 08 08:38:20 2008 +0000
committer Evan Cheng <evan.cheng@apple.com> Mon Sep 08 08:38:20 2008 +0000
tree 505d40a674f18a2e2bab0818a733142e1ce3504a
parent 24e3a90904601fc6caf9d1b8c1be965806d529ae

Add fast isel physical register definition support.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55892 91177308-0d34-0410-b5e6-96231b3b80d8

lib/CodeGen/SelectionDAG/FastISel.cpp

diff --git a/lib/CodeGen/SelectionDAG/FastISel.cpp b/lib/CodeGen/SelectionDAG/FastISel.cpp
index 19cb922..58467b8 100644
--- a/lib/CodeGen/SelectionDAG/FastISel.cpp
+++ b/lib/CodeGen/SelectionDAG/FastISel.cpp
@@ -576,7 +576,16 @@
   unsigned ResultReg = createResultReg(RC);
   const TargetInstrDesc &II = TII.get(MachineInstOpcode);
 
-  BuildMI(MBB, II, ResultReg).addReg(Op0);
+  if (II.getNumDefs() >= 1)
+    BuildMI(MBB, II, ResultReg).addReg(Op0);
+  else {
+    BuildMI(MBB, II).addReg(Op0);
+    bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
+                                         II.ImplicitDefs[0], RC, RC);
+    if (!InsertedCopy)
+      ResultReg = 0;
+  }
+
   return ResultReg;
 }
 
@@ -586,7 +595,15 @@
   unsigned ResultReg = createResultReg(RC);
   const TargetInstrDesc &II = TII.get(MachineInstOpcode);
 
-  BuildMI(MBB, II, ResultReg).addReg(Op0).addReg(Op1);
+  if (II.getNumDefs() >= 1)
+    BuildMI(MBB, II, ResultReg).addReg(Op0).addReg(Op1);
+  else {
+    BuildMI(MBB, II).addReg(Op0).addReg(Op1);
+    bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
+                                         II.ImplicitDefs[0], RC, RC);
+    if (!InsertedCopy)
+      ResultReg = 0;
+  }
   return ResultReg;
 }
 
@@ -596,7 +613,15 @@
   unsigned ResultReg = createResultReg(RC);
   const TargetInstrDesc &II = TII.get(MachineInstOpcode);
 
-  BuildMI(MBB, II, ResultReg).addReg(Op0).addImm(Imm);
+  if (II.getNumDefs() >= 1)
+    BuildMI(MBB, II, ResultReg).addReg(Op0).addImm(Imm);
+  else {
+    BuildMI(MBB, II).addReg(Op0).addImm(Imm);
+    bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
+                                         II.ImplicitDefs[0], RC, RC);
+    if (!InsertedCopy)
+      ResultReg = 0;
+  }
   return ResultReg;
 }
 
@@ -606,7 +631,15 @@
   unsigned ResultReg = createResultReg(RC);
   const TargetInstrDesc &II = TII.get(MachineInstOpcode);
 
-  BuildMI(MBB, II, ResultReg).addReg(Op0).addFPImm(FPImm);
+  if (II.getNumDefs() >= 1)
+    BuildMI(MBB, II, ResultReg).addReg(Op0).addFPImm(FPImm);
+  else {
+    BuildMI(MBB, II).addReg(Op0).addFPImm(FPImm);
+    bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
+                                         II.ImplicitDefs[0], RC, RC);
+    if (!InsertedCopy)
+      ResultReg = 0;
+  }
   return ResultReg;
 }
 
@@ -616,7 +649,15 @@
   unsigned ResultReg = createResultReg(RC);
   const TargetInstrDesc &II = TII.get(MachineInstOpcode);
 
-  BuildMI(MBB, II, ResultReg).addReg(Op0).addReg(Op1).addImm(Imm);
+  if (II.getNumDefs() >= 1)
+    BuildMI(MBB, II, ResultReg).addReg(Op0).addReg(Op1).addImm(Imm);
+  else {
+    BuildMI(MBB, II).addReg(Op0).addReg(Op1).addImm(Imm);
+    bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
+                                         II.ImplicitDefs[0], RC, RC);
+    if (!InsertedCopy)
+      ResultReg = 0;
+  }
   return ResultReg;
 }
 
@@ -626,7 +667,15 @@
   unsigned ResultReg = createResultReg(RC);
   const TargetInstrDesc &II = TII.get(MachineInstOpcode);
   
-  BuildMI(MBB, II, ResultReg).addImm(Imm);
+  if (II.getNumDefs() >= 1)
+    BuildMI(MBB, II, ResultReg).addImm(Imm);
+  else {
+    BuildMI(MBB, II).addImm(Imm);
+    bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
+                                         II.ImplicitDefs[0], RC, RC);
+    if (!InsertedCopy)
+      ResultReg = 0;
+  }
   return ResultReg;
 }
 
@@ -637,6 +686,14 @@
   unsigned ResultReg = createResultReg(SRC);
   const TargetInstrDesc &II = TII.get(TargetInstrInfo::EXTRACT_SUBREG);
   
-  BuildMI(MBB, II, ResultReg).addReg(Op0).addImm(Idx);
+  if (II.getNumDefs() >= 1)
+    BuildMI(MBB, II, ResultReg).addReg(Op0).addImm(Idx);
+  else {
+    BuildMI(MBB, II).addReg(Op0).addImm(Idx);
+    bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
+                                         II.ImplicitDefs[0], RC, RC);
+    if (!InsertedCopy)
+      ResultReg = 0;
+  }
   return ResultReg;
 }